Nonvolatile 8-bit Booth multiplier based on RRAM
A non-volatile, multiplier technology, used in instruments, static memory, digital memory information, etc., can solve the problem of lack of non-volatile multiplier design, reduce read and write power consumption and leakage power consumption, The effect of fast power-on speed and high storage density
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[0066] 1 Improvement to the traditional radix-4Booth algorithm
[0067] For an 8-bit Booth multiplier, each partial product generated by Booth encoding needs to extend the sign bit to 16 bits at the highest bit, which means that more memory is needed to store these redundant sign bits , Traditional extensions such as figure 2 As shown, the black dots represent the sign bit and the white dots represent the data bit.
[0068] In fact, these redundant sign bits can be reduced by the following methods:
[0069] A 15-bit partial product complement code can be expressed as follows:
[0070] S S S S S S S S Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z 1
[0071] This form of redundancy can be rewritten as:
[0072] -S Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z 1
[0073] because
[0074] -s*2 14 +(s*2 13 +s*2 12 +s*2 11 +s*2 10 +s*2 9 +s*2 8 )
[0075] =-s*2 14 +s*(2 14 -2 8 )=-s*2 8 (2-4)
[0076] In this way, for an 8-bit radix-4 Booth multiplier, four partial products can be expressed image 3 .
[0077] But in digital circuit d...
Embodiment 1
[0116] Overall simulation and functional verification of the multiplier of the present invention
[0117] The design environment of the multiplier in this embodiment is the Virtuoso Schematic tool of Cadence, and the simulation environment uses a low-threshold voltage 45nm process library (GDPK045), and the working voltage is V dd =0.8V, working clock CLK=357MHz. For the RRAM model used, please refer to P. Chen and S. Yu, "Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design," in IEEETransactions on Electron Devices, vol.62, no.12, pp.4022-4028 ,Dec.2015.
[0118] In the RRAM model of this embodiment, we modified some parameters so that the RRAM of RRAM HRS ≈100R LRS , To meet the design requirements of our multipliers.
[0119] Transient simulation results:
[0120] The transient simulation results are as Figure 23 Shown. The multiplicand A is input from the external register as "01101101", and the multiplier B is configured as "-1, +1, -1, +1" i...
Embodiment 2
[0123] 1 Performance comparison of a single multiplier
[0124] In order to fully evaluate the performance of the 8-bit new non-volatile Booth multiplier, Table 3 shows the speed, area, power consumption, and non-volatility of the 1-row multiplier and the 2-row multiplier, and compare them with [1 ] (See S. Kuang, J. Wang, and C. Guo, "Modified booth multipliers with a regular partial product array," IEEETransactions on Circuits and Systems II: Express Briefs, vol.56, no.5, pp.404–408 ,May 2009.) and [2] (see W. Liu, L. Qian, C. Wang, H. Jiang, J. Han, and F. Lombardi, "Design of approximate radix-4booth multipliers for error-tolerantcomputing," IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435–1441, Aug 2017.) The proposed 8-bit multiplier was compared. At the same time, we designed a traditional Booth multiplier using the same process library GDPK045, and evaluated its speed, area, and power consumption, so as to compare the difference between the new multiplier and the...
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