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Method, device and system for correcting establishment time violation

A technology for establishing time and logic devices, applied in electrical components, pulse technology, electronic switches, etc., to solve problems such as increasing leakage power consumption

Pending Publication Date: 2021-03-26
SHENZHEN DAPU MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method can effectively reduce device delay and thereby reduce path delay, it will increase leakage power consumption

Method used

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  • Method, device and system for correcting establishment time violation
  • Method, device and system for correcting establishment time violation
  • Method, device and system for correcting establishment time violation

Examples

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Embodiment Construction

[0067] The core of the present invention is to provide a method, device and system for correcting establishment time violations, which can reduce the increase of leakage power consumption on the basis of faster correction of establishment time, and improve the efficiency of correcting establishment time violations.

[0068] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0069] Please refer to ...

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Abstract

The invention discloses a method, device and system for correcting establishment time violation, and the method comprises the steps: sequentially replacing logic devices with replacement logic devicesaccording to delay power consumption weight ratios in a descending order when the logic devices on an establishment time violation path are replaced; and updating the path margin to the sum of the path margin and the delay reduction amount of the replaced logic device after each replacement until the updated path margin is greater than 0 or all logic devices are replaced. Visibly, on the basis ofthe technology of replacing the logic devices of the same type, the power consumption of replacing the logic devices is also considered, and the larger the delay power consumption weight ratio is, the larger the delay gain obtained after the logic devices are replaced is, so that the increased electric leakage power consumption is less; visibly the device replacement is carried out according to the descending order of the delay power consumption weight ratios, so that the increase of the leakage power consumption can be reduced on the basis of short correction and establishment time, and theefficiency of violation of the correction and establishment time is improved.

Description

technical field [0001] The invention relates to the technical field of chip timing, in particular to a method, device and system for correcting setup time violations. Background technique [0002] As the market's requirements for chip power consumption become higher and higher, more and more voltage domains are divided in chip low-power consumption design. In a low-power design, signals are transmitted between different voltage domains, and there are inevitably timing violation paths across multiple voltage domains, and setup time violations are one of them. Setup time is the time the data must be stable before the device is sampled by the clock edge. Take the synchronous circuit as an example, please refer to figure 1 , figure 1 It is a simplified structure diagram of a synchronous circuit. [0003] In static timing analysis, the timing path from clock control flip-flop to flip-flop must satisfy the following two expressions: [0004] Expression 1: Tclk1+T1_cq+Tdelay_s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/28
CPCH03K17/28
Inventor 韦秋初黄运新
Owner SHENZHEN DAPU MICROELECTRONICS CO LTD
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