A method and a
system for using synthetic partitioning constraints to impose design patterns containing desired design features (e.g.,
distributed logic for a threaded, multicore based computation) onto logical architectures (LA) specifying an implementation neutral computation. The LA comprises computational specifications and related logical constraints (i.e., defined by logical assertions) that specify provisional loops and provisional partitionings of those loops. The LA contains virtually no
programming language constructs. Synthetic partitioning constraints add implementation specific design patterns. They define how to find frameworks with desired design features, how to reorganize the LA to accommodate the frameworks, and how to map the computational
payload from the LA into the frameworks. The
advantage of synthetic partitioning constraints is they allow implementation neutral computations to be transformed into custom implementations that
exploit the high capability features of arbitrary execution platform architectures such as multicore, vector, GPU, FPGA, virtual, API-based and others.