22results about "Amplifiers with memory effect compensation" patented technology

According to embodiments, a method performed by an electronic device includes: identifying a channel bandwidth; identifying one or more active DPD units among a plurality of DPD units of a digital pre-distortion (DPD) circuit based on the channel bandwidth and amount of resource allocated within the channel bandwidth; generating a DPD output signal of the DPD circuit based on the one or more active DPD units; generating an amplifier output signal based on the DPD output signal of the DPD circuit, a digital-to-analog converter (DAC), and a power amplifier (PA). While the DPD output signal is generated, at least one DPD unit different from the one or more active DPD units among the plurality of DPD units of the DPD circuit is deactivated.

A method carried out by an electronic device, according to the embodiments, may comprise a step for identifying a channel bandwidth. The method may comprise the steps of: on the basis of the channel bandwidth and a quantity of resources allocated in the channel bandwidth, identifying one or more active digital pre-distortion (DPD) units among a plurality of DPD units of a DPD circuit; generating a DPD output signal of the DPD circuit on the basis of the one or more active DPD units; and generating an amplifier output signal on the basis of the DPD output signal of the DPD circuit, a digital-to-analog converter (DAC), and a power amplifier (PA). While the DPD output signal is being generated, at least one DPD unit, among the plurality of DPD units of the DPD circuit, which is different from the one or more active DPD units may be deactivated.

Memory distortion neutralization in a power amplifier circuit (58) is provided. The power amplifier circuit (58) includes one or more amplifier stages (40, 42) each configured to amplify a radio frequency (RF) signal based on a time-variant modulated voltage received at a respective collector node. Notably, each of the amplifier stages (40, 42) can inherently cause a derivative of the time-variant modulated voltage (a.k.a. a modulated current) to be leaked from the respective collector node into a respective input node, which can create unwanted remodulation terms that can degrade an adjacent channel leakage ratio (ACLR) of the power amplifier circuit (58). Herein, a neutralization circuit (54, 60) is configured to inject a neutralization current to the respective input node to cancel at least a portion of the leaked modulated current.

Provided is a method for implementing a digital predistortion scheme. The method includes obtaining (S210) artificial-intelligence-digital-predistortion (AI-DPD) schemes of eight neural-networks by using a unified digital predistortion (DPD) hardware structure and using software configuration.

In one example, a device comprises: an operational amplifier (opamp) to amplify a difference between a reference voltage and a feedback voltage and output a bias signal based on the difference; a emulation device coupled to the opamp, the emulation device having a gate terminal for receiving the bias signal; and an output stage coupled to the emulation device to output a regulated voltage, the output stage comprising a pass device and a plurality of feedback devices coupled to the pass device, wherein a selected number of the plurality of feedback devices are to be activated based at least in part on an output power level of a power amplifier, the power amplifier receiving the regulated voltage.

A power amplification system (7) is provided with: power amplifiers (2A, 2B); a switched capacitor circuit (20) configured so as to generate a plurality of discrete voltages on the basis of the regulated voltage supplied from the preregulator circuit (10); an output switching circuit (30) configured to selectively output at least one of the plurality of discrete voltages to the power amplifier (2A); and a DPD circuit (71) configured to predistort the high-frequency signals (RF1 and RF2), the preregulator circuit (10) configured to convert an input voltage into a regulated voltage, output the regulated voltage to the switched capacitor circuit (20), and output the regulated voltage to the power amplifier (2B) without passing through the switched capacitor circuit (20), and the DPD circuit (71) predistorts the high-frequency signal (RF1) using a first mathematical model, and outputs the predistorted high-frequency signal (RF2) using a second mathematical model. And pre-distorting the high-frequency signal (RF2) using a second mathematical model, or not pre-distorting the high-frequency signal (RF2).

In one example, an apparatus includes: an operational amplifier (opamp) to amplify a difference between a reference voltage and a feedback voltage and output a bias signal based on the difference; a replica device coupled to the opamp, the replica device having a gate terminal to receive the bias signal; and an output stage coupled to the replica device and to output a regulated voltage, the output stage having a pass device and a plurality of feedback devices coupled to the pass device. A selected number of the plurality of feedback devices can be enabled based at least in part on an output power level of a power amplifier that is to receive the regulated voltage.

An electronic device includes a processor that converts AM-AM data and AM-PM data into complex domains for each of a plurality of different amplitudes to acquire a plurality of preprocessed data parts, converts the plurality of preprocessed data parts into a time domain to generate a plurality of filters for each of a plurality of different amplitudes, generates an output signal by performing a convolution on an input signal with the plurality of filters, and models a non-linear memory system using the input signal and the output signal.

An apparatus may be configured to receive a signal to be transmitted via an array of antennas by a zero-forcing precoder, wherein the signal is processed by the linear precoder based on one or more input power criteria for power amplifiers of the array of antennas; apply a distortion reducing matrix to the processed signal, wherein the distortion reducing matrix is trained to reduce the distortion at each output of the power amplifiers based on minimizing an error signal corresponding to a difference between measured and calculated outputs of the power amplifiers after a coupling effect between the power amplifiers based on the applied matrices; and provide an output of the distortion reducing matrix to be used in digital pre-distortion processing of an input signal for the power amplifiers.

According to embodiments, a method performed by an electronic device includes: identifying a channel bandwidth; identifying one or more active DPD units among a plurality of DPD units of a digital pre-distortion (DPD) circuit based on the channel bandwidth and amount of resource allocated within the channel bandwidth; generating a DPD output signal of the DPD circuit based on the one or more active DPD units; generating an amplifier output signal based on the DPD output signal of the DPD circuit, a digital-to-analog converter (DAC), and a power amplifier (PA). While the DPD output signal is generated, at least one DPD unit different from the one or more active DPD units among the plurality of DPD units of the DPD circuit is deactivated.

Embodiments of the present disclosure provide digital predistortion method and digital predistortion apparatus. The digital predistortion method for power amplifier, PA, comprises: in accordance with a predicted traffic condition associated with a future time, determining PA related parameters for the future time; and applying the determined PA related parameters when the future time comes.

A distortion apparatus for a power amplifier comprises: pre-distortion circuitry that comprises a memory polynomial look-up-table (LUT) circuit; and post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier. The pre-distortion circuitry comprises a plurality of LUTs. Each LUT corresponds to a different memory depth of a memory polynomial of a Volterra series. Each LUT indexed by an instantaneous power of an input sample delayed by an amount corresponds to a respective memory depth of each LUT. An output of the memory polynomial LUT circuit corresponds to a summation of an output of each LUT multiplied by the input sample delayed by the amount corresponding to the respective memory depth of each LUT, and an output of the pre-distortion circuitry is provided to the power amplifier.

Provided is a method for implementing a digital predistortion scheme. The method includes obtaining (S210) artificial-intelligence-digital-predistortion (AI-DPD) schemes of eight neural-networks by using a unified digital predistortion (DPD) hardware structure and using software configuration.

Memory distortion neutralization in a power amplifier circuit (58) is provided. The power amplifier circuit (58) includes one or more amplifier stages (40, 42) each configured to amplify a radio frequency (RF) signal based on a time-variant modulated voltage received at a respective collector node. Notably, each of the amplifier stages (40, 42) can inherently cause a derivative of the time-variant modulated voltage (a.k.a. a modulated current) to be leaked from the respective collector node into a respective input node, which can create unwanted remodulation terms that can degrade an adjacent channel leakage ratio (ACLR) of the power amplifier circuit (58). Herein, a neutralization circuit (54, 60) is configured to inject a neutralization current to the respective input node to cancel at least a portion of the leaked modulated current.

In one example, an apparatus includes an operational amplifier (opamp) to amplify a difference between a reference voltage and a feedback voltage and output a bias signal based on the difference; a replication device, the replication device being coupled to the opamp, the replication device having a gate terminal for receiving the bias signal; and an output stage coupled to the replica device and for outputting a regulated voltage, the output stage having a pass device and a plurality of feedback devices coupled to the pass device. A selected number of feedback devices of the plurality of feedback devices may be enabled based at least in part on an output power level of a power amplifier that is to receive the regulated voltage.

A digital pre-distortion achieving near ideal spectral regrowth suppression with a bandlimited loopback. To eliminate mismatch between the bandwidth of the pre-distortion model terms and the bandwidth of the signal used to determine the model a band limiting operation may be applied to both the loopback signal and the input to the power amplifier used for estimating the pre-distortion coefficients. In addition, oversampling may be performed in the digital domain to avoid aliasing in the nonlinear terms of the pre-distortion model.

A digital pre-distortion achieving near ideal spectral regrowth suppression with a bandlimited loopback. To eliminate mismatch between the bandwidth of the pre-distortion model terms and the bandwidth of the signal used to determine the model a band limiting operation may be applied to both the loopback signal and the input to the power amplifier used for estimating the pre-distortion coefficients. In addition, oversampling may be performed in the digital domain to avoid aliasing in the nonlinear terms of the pre-distortion model.

Embodiments of the present disclosure provide digital predistortion method and digital predistortion apparatus. The digital predistortion method for power amplifier, PA, comprises: in accordance with a predicted traffic condition associated with a future time, determining PA related parameters for the future time; and applying the determined PA related parameters when the future time comes.

A power amplification system includes: a first power amplifier configured to amplify a first radio-frequency signal; a second power amplifier configured to amplify a second radio-frequency signal; a switched-capacitor circuit configured to generate multiple discrete voltages based on a regulated voltage supplied from a pre-regulator; an output switch circuit configured to selectively output at least one of the multiple discrete voltages as a first power supply of the first power amplifier; and a digital predistortion circuit configured to predistort the first and second radio-frequency signals. The pre-regulator circuit is configured to convert an input voltage to the regulated voltage. The regulated voltage is provided as a second power supply of the second power amplifier without using the switched-capacitor circuit. The digital predistortion circuit predistorts the first radio-frequency signal by using a first mathematical-expression model for digital predistortion. The first mathematical-expression model is not applied on the second radio-frequency signal.

A power amplification system (7) comprises the following features: power amplifiers (2A, 2B); a switching capacitor circuit (20) configured to generate several discrete voltages based on a regulated voltage supplied by a pre-regulator circuit (10); an output switch circuit (30) configured to selectively output at least one of the several discrete voltages to the power amplifier (2A); and a DPD circuit (71) configured to pre-distort high-frequency signals (RF1, RF2). The pre-regulator circuit (10) is configured to convert an input voltage into a regulated voltage, output the regulated voltage to the switching capacitor circuit (20), and output the regulated voltage directly to the power amplifier (2B) without using the switching capacitor circuit (20).The DPD circuit (71) uses a first mathematical expression model to pre-distort the high-frequency signal (RF1) and uses a second mathematical expression model to pre-distort the high-frequency signal (RF2), or does not pre-distort the high-frequency signal (RF2).

An apparatus may be configured to receive a signal to be transmitted via an array of antennas by a zero-forcing precoder, wherein the signal is processed by the linear precoder based on one or more input power criteria for power amplifiers of the array of antennas; apply a distortion reducing matrix to the processed signal, wherein the distortion reducing matrix is trained to reduce the distortion at each output of the power amplifiers based on minimizing an error signal corresponding to a difference between measured and calculated outputs of the power amplifiers after a coupling effect between the power amplifiers based on the applied matrices; and provide an output of the distortion reducing matrix to be used in digital pre-distortion processing of an input signal for the power amplifiers.

An apparatus may be configured to receive a signal to be transmitted via an array of antennas by a zero-forcing precoder, wherein the signal is processed by the linear precoder based on one or more input power criteria for power amplifiers of the array of antennas; apply a distortion reducing matrix to the processed signal, wherein the distortion reducing matrix is trained to reduce the distortion at each output of the power amplifiers based on minimizing an error signal corresponding to a difference between measured and calculated outputs of the power amplifiers after a coupling effect between the power amplifiers based on the applied matrices; and provide an output of the distortion reducing matrix to be used in digital pre-distortion processing of an input signal for the power amplifiers.