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Verification system and method for cooperative work between integrated circuit modules

A circuit module and integrated circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as the inability to establish a collaborative work verification environment between circuit modules, and the detection lag of core circuit module interconnection function problems.

Active Publication Date: 2020-06-30
北京燧原智能科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Embodiments of the present invention provide a verification system and verification method for cooperative work between integrated circuit modules to solve the problem that the verification environment for cooperative work between circuit modules cannot be established when the interconnection circuit, memory, and upper-layer circuit integration wiring are not completed in the design of the interconnection circuit problems, avoiding the phenomenon of lagging in the detection of core circuit module interconnection function problems, and saving human resources for verification

Method used

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  • Verification system and method for cooperative work between integrated circuit modules
  • Verification system and method for cooperative work between integrated circuit modules
  • Verification system and method for cooperative work between integrated circuit modules

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Embodiment 1

[0029] figure 1 A schematic structural diagram of a verification system for cooperating among integrated circuit modules provided by Embodiment 1 of the present invention. This embodiment is applicable to verifying the cooperating ability between core function modules under the condition that the interconnection circuit of the core circuit modules is not completed. Circumstances for verification. Such as figure 1 As shown, the verification system for cooperating among integrated circuit modules specifically includes: a stimulus model 10 , a function simulation model 20 , an interconnection circuit model 30 , a memory model 40 and a scoreboard 50 . in,

[0030] The stimulus model 10 is used to generate the command set of the circuit module under test 60, the interconnection circuit model configuration information and the memory model configuration information, and send the command set to the host circuit module 61 and the function simulation model 20 respectively, and transfe...

Embodiment 2

[0080] image 3 Embodiment 2 of the present invention provides a flow chart of a method for verifying collaborative work between integrated circuit modules. This embodiment is applicable to verifying the collaborative work capability between core function modules under the condition that the interconnection circuit of the core circuit modules is not completed. The case of verification. The method can be executed by a verification system that cooperates among integrated circuit modules provided by an embodiment of the present invention. The system can be implemented in software and / or hardware, and can generally be integrated into a computer.

[0081] Such as image 3 As shown, the method of this embodiment specifically includes:

[0082] S210. Generate the instruction set of the circuit module under test, the interconnection circuit model configuration information, and the memory model configuration information through the excitation model, and send the instruction set to th...

Embodiment 3

[0123] Figure 4 It is a schematic structural diagram of a verification system for cooperating among integrated circuit modules provided by Embodiment 3 of the present invention. This embodiment provides a specific implementation manner.

[0124] refer to Figure 4 , the circuit under test in this embodiment may be a computing unit cluster (CLUSTER) in an artificial intelligence chip, and each CLUSTER has a host interface circuit and a slave interface circuit. The data transmission protocol can be AXI4.0 (Advanced eXtensible Interface is a high-performance, high-bandwidth, low-latency on-chip bus in the AMBA-Advanced Microcontroller Bus Architecture protocol proposed by ARM). Specifically, the tested circuits are two CLUSTER instances, respectively C0 and C1, wherein C0 is used as a master circuit module, and C1 is used as a slave circuit module.

[0125] First, the stimulus model writes the set of instructions into C0. Secondly, C0 executes the instruction set, and writes...

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Abstract

The embodiment of the invention discloses a verification system and method for cooperative work between integrated circuit modules. The verification system comprises an excitation model, a function simulation model, an interconnection circuit model, a memory model and a scoreboard, and the interconnection circuit model is used for realizing an interconnection function of a host circuit module anda slave circuit module in a tested circuit according to interconnection circuit configuration information; and the scoreboard is used for realizing verification of cooperative work between the host circuit module and the slave circuit module according to the operation expectation value, the host operation actual value and the slave operation actual value. By adopting the verification system for cooperative work between the integrated circuit modules, the interconnection function of the tested circuit and the verification of the cooperative work capability of multiple modules can be completed with high quality under the condition of no interconnection circuit, memory and upper-layer integrated connecting wire, so that the problem of the tested circuit can be found and solved earlier.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of integrated circuits, and in particular to a verification system and verification method for cooperating among integrated circuit modules. Background technique [0002] In chip design, especially 5G and artificial intelligence chips, large-scale interconnection of core circuit modules is essential. [0003] In the early development of integrated circuits, more than 70% of the workload is in the verification stage. However, the relevant verification environment has the following problems: in the interconnection circuit design, when the memory design and circuit integration are not completed, it is impossible to establish a verification environment for the collaborative work of the circuit modules, and then it is impossible to verify the collaborative work function of the core circuit modules. Circuit modules cannot be distributed in high quality individually. Correspondingly, ver...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3308
Inventor 杨兵李振李春红
Owner 北京燧原智能科技有限公司
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