Verification method and system for second-level cache interface protocol

A technology of secondary cache and interface protocol, applied in the field of multi-core verification, can solve the problems of low debugging efficiency, consuming a lot of time and energy, affecting the progress of the project, etc., to achieve the effect of improving debugging efficiency and effective and rapid positioning

Pending Publication Date: 2022-03-08
GUANGDONG STARFIVE TECH LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Aiming at the deficiencies of the prior art, the present invention discloses a verification method and system of a secondary cache interface protocol, which is used to solve the problem that in multi-core verification, there is usually a global checker that reports an error when an error occurs in t

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  • Verification method and system for second-level cache interface protocol

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Experimental program
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Embodiment 1

[0047] This embodiment provides a verification method of a secondary cache interface protocol. When the method checks the read data, it records the key information of each read request, and compares the data of the memory model with the DUT data when the read data is returned, and performs When the wake-up request is checked, it is checked through the protocol agreement; when the method checks the data of the D or C channel, the data of the memory model is compared with the DUT data, and when the rationality of the B / C channel is checked, it is judged according to the content of the secondary cache .

[0048] This embodiment checks the read data, records key information such as the address of each read request, flag bits, etc., when the read data returns, query the recorded read request information through the flag bits, and read the data of the memory model according to the queried address , and compared with the DUT data.

[0049] The check of the wake-up request in this em...

Embodiment 2

[0055] At the specific implementation level, this embodiment provides a secondary cache interface structure, such as figure 1 Shown:

[0056] In this embodiment, the interface between the secondary cache and the core is a custom protocol, including a read request signal sent from the core, a write request signal, a wake-up signal returned by the secondary cache, and a read-back data signal. The secondary cache can be connected to multiple cores, and the number of cores can be configured.

[0057] In this embodiment, the interface between the second-level cache and the third-level cache or memory is a tilelink bus protocol interface. This protocol is mainly used in the RISCV architecture and includes five channels of A / B / C / D / E.

[0058] In this embodiment, channel A is a read-write request channel, which includes information such as read-write addresses, write data, and request types.

[0059] In this embodiment, channel B is a snoop request channel, and includes information ...

Embodiment 3

[0065] At the specific implementation level, this embodiment provides a checker structure, such as figure 2 Shown:

[0066] In this embodiment, a custom interface checker is used to monitor the correctness of the custom interface signal.

[0067] The inspection process of the read data in this embodiment:

[0068] a. When the core sends a read request signal to the L2 cache, the checker stores the read address, read flag, and read request type into the read request queue;

[0069] b. When the second-level cache returns the read data, monitor the flag bit of the returned information and traverse the read request queue at the same time. If there is a valid request flag bit in the read request queue that is the same as the flag bit of the returned information, it means that the returned data corresponds to the read request;

[0070] c. Obtain the address and read request type information from the read request with the same flag bit. If the read request type is a write upgrade...

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Abstract

The invention relates to the technical field of multi-core verification, in particular to a verification method and system for a second-level cache interface protocol, and the method comprises the steps: recording key information of each read request when read data is checked, comparing data of a memory model with DUT data when the read data is returned, and checking through protocol agreement when a wake-up request is checked; according to the method, when D or C channel data are checked, data of a memory model is compared with DUT data, and when B/C channels are subjected to rationality check, judgment is carried out according to second-level cache content. According to the method, the second-level cache interface protocol is verified, when data in the protocol goes wrong, error information is reported in real time, it is not needed to wait for a global checker to report errors, error codes can be more effectively and rapidly positioned, and the debugging efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of multi-core verification, in particular to a verification method and system for a secondary cache interface protocol. Background technique [0002] In a multi-core system, the verification of the second-level cache is very important. In multi-core verification, there is usually a global checker that reports an error when there is an error in the memory access instruction data. At this time, the data has already passed the third-level cache. For the second-level cache and the first-level cache, it takes a lot of time and effort to trace back to the original error, and the debugging efficiency is low, which affects the project progress. [0003] This article verifies the interface protocol of the second-level cache, including the custom protocol between the second-level cache and the core, and the Tilelink bus protocol between the second-level cache and the third-level cache / memory. For the verification of ...

Claims

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Application Information

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IPC IPC(8): G06F11/26
CPCG06F11/26
Inventor 沈秀红
Owner GUANGDONG STARFIVE TECH LTD
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