System, method and medium for realizing cache consistency of PCIe equipment

Abstract

Provided are a system, method and medium for implementing cache consistency of a PCIe device, the system comprising: a CPU cache master controller configured to send a first read-write request of a CPU for a first address to a memory cache slave controller through a cache command of an internal bus; the memory cache slave controller is configured to update the state of the memory cache line of the first address according to the state of the memory cache line of the first address of the first read-write request, and send the first address and a command for updating the state of the cache line of the PCIe equipment to be the first state to the input / output bridge controller through a cache command of an internal bus; the input / output bridge controller is configured to send the first address and a command for updating the state of the cache line of the PCIe equipment to be in a first state to the PCIe equipment through a first PCIe bus message, receive first data from the first address of the PCIe equipment through a second PCIe bus message and receive a response for updating the state of the cache line of the PCIe equipment to be in the first state, and the cache command of the internal bus is sent to the memory cache slave controller.

Description

technical field [0001] The present application relates to the field of integrated circuits, and more particularly, to a system, method and medium for implementing cache coherency of PCIe devices. Background technique [0002] Peripheral Component Interconnect Express (PCIe for short) bus is a computer bus Peripheral Component Interconnect (PCI) standard, which follows the existing PCI programming concepts and communication standards, but based on faster serial communication system. The PCIe bus should only be used for internal interconnection. Since the PCIe system is based on the existing PCI system, the existing PCI system can be converted into the PCIe system only by modifying the physical layer without modifying the software. The PCIe bus has a faster rate to replace almost all existing internal buses (including Accelerated Graphics Port (AGP) bus and PCI bus). [0003] The PCIe bus link uses an end-to-end data transmission method, such as figure 1 as shown, figure ...

AI Technical Summary

Problems solved by technology

[0004] The traditional PCIe protocol does not support PCIe endpoint (end-point, EP) device maintenance and data consistency between memory and central processing unit (CPU)

However, in the case where the EP device and the CPU have their own caches, there may be a copy of the same data in both caches, but when the two independently modify the copies of the same data stored in their respective caches , which may lead to inconsistent copies of the same data between different caches

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