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Self-adaptive testing method and device of CPU cache memory

A test method and memory technology, applied in the direction of static memory, instrument, etc., can solve the problem of inability to adjust the EMA of different chips

Active Publication Date: 2016-06-15
FUZHOU ROCKCHIP SEMICON
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 2. It is impossible to automatically adjust the EMA of different chips and perform automatic classification

Method used

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  • Self-adaptive testing method and device of CPU cache memory

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Embodiment Construction

[0056] The self-adaptive testing method of CPUcache memory of the present invention is to set the frequency configuration corresponding to the test target frequency earlier before the test, and the frequency usually set is exactly the highest frequency that the storage unit may run to in practical applications; after starting the test, pass The jtag interface is poured into the bist start command; the jtag command is converted into a direct control signal after protocol analysis; the bist test process with EMA scanning is carried out through the direct control signal, if the best EMA is found in the bist test process, then It is judged that the test is passed, and the internal EEPROM will store the best EMA configuration value at this frequency for use when the chip enters the normal working mode; otherwise, it is judged that the test has failed, and the chip is classified as a chip that does not meet the requirements.

[0057] The adaptive testing method of the CPUcache memory...

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Abstract

The invention provides a self-adaptive testing method and device of CPU cache memory. The method includes: setting the frequency allocation corresponding to a test target frequency before testing; when testing starts, injecting a bist start command through a jtag interface; conducting protocol parsing on a jtag command into a direct control signal; performing an EMA (extra margin adjustment) scanning equipped bist testing process through the direct control signal, if optimal EMA is found in a bist testing process, judging the test passes, at the same time internal EEPROM can store an optimal EMA configuration value under the frequency for a chip to use while entering a normal work mode; otherwise judging the test fails, and classifying the chip into an unsatisfactory chip. The optimal EMA value is obtained through testing to serve the configuration use of the chip during normal work, so that the chip can work under the optimal EMA value specific to itself and acquire an equilibrium point of the best memory performance and stability.

Description

technical field [0001] The invention relates to an adaptive testing method and device for a CPUcache memory. Background technique [0002] The highest CPU frequency of the chip directly determines the performance of the chip, and the SRAM (Static RAM, static random access memory) that constitutes the cache (cache memory) in the CPU is usually the bottleneck of the limit frequency. The SRAM memory unit in the chip is a circuit that is very sensitive to the manufacturing process. During the chip manufacturing process, chips at different positions on each batch and each wafer may have different performances due to deviations in the manufacturing process. However, the current testing technology uses the worst process among the deviations of all manufacturing processes as the test setting to ensure that as many chips as possible can pass the test. [0003] In the recent SRAM design, an EMA (ExtraMarginAdjustment) port configuration has been added. This port has 3 bits, which can...

Claims

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Application Information

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IPC IPC(8): G11C29/56
CPCG11C29/56G11C29/56008
Inventor 廖裕民吕小兵
Owner FUZHOU ROCKCHIP SEMICON
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