Configuration method applied to coarse-grained reconfigurable array

Abstract

The invention discloses a configuration method applied to a coarse-grained reconfigurable array, which aims at a coarse-grained reconfigurable array with a certain scale, and comprises a configuration defining scheme taking data links as basic description objects, a corresponding configuration generating scheme and a corresponding configuration mapping scheme. The configuration defining scheme includes that a program corresponds to a plurality of configurations, each configuration corresponds to one data link, and each data link consists of a plurality of reconfigurable cells with data dependence relations. Compared with a traditional scheme taking RCs (reconfigurable cells) as basic description objects, the configuration defining scheme is capable of concealing interlinking information among the RCs and providing a larger configuration information compression space, thereby being beneficial to decrease of the total amount of configuration and time for switching configuration. Besides, the configuration of one description data link consists of a route, a functional configuration and one or more data configurations, the data configurations share one route and functional configuration information, and switching of one configuration includes one-time or multiple switching of the data configuration after one-time switching of the corresponding route and the functional configuration.

Description

technical field [0001] The invention relates to the field of embedded reconfigurable design, in particular to a configuration method proposed for a coarse-grained reconfigurable computing array. Background technique [0002] Reconfigurable computing is currently a research hotspot in the field of high-performance parallel computing. It can achieve a good trade-off in performance, power consumption and flexibility. Coarse-grained reconfigurable computing arrays are the computing Components have massive computing resources and sufficient routing resources. By rationally configuring the functions and routing of their computing units, the parallelism of computing can be fully explored. Compared with general-purpose processors, the computing efficiency of reconfigurable computing arrays has been greatly improved, so it is especially suitable for computing-intensive and data-intensive applications, especially graphics and video decoding applications. [0003] According to differe...

AI Technical Summary

Problems solved by technology

However, due to the continuous expansion of the array scale and the continuous increase of configuration files, in the process of processing high-performance parallel computing applications such as video codecs in reconfigurable systems, the overhead of configuration switching is often the bottleneck restricting its performance improvement, and this overhead Dominates the power consumption overhead of reconfigurable multimedia systems

Images