Wiring delay deviation fast calibration method of arbitration-type PUF based on FPGA

Abstract

The invention discloses a wiring delay deviation fast calibration method of an arbitration-type PUF based on an FPGA. According to the technical scheme, fast calibration of delay deviation is achieved by an automatic adjusting circuit which is composed of one counter, one comparator, one dichotomy computing module and one excitation storage module. After input read signals become effective, the excitation storage module outputs stored excitations to the PUF from the first excitation to the last excitation, and afterwards sets excitation marking signals connected with the counter to be effective. When input adjusting completion signals become effective, the counter conducts zero clearing, and begins to conduct accumulative counting on responses of the PUF, and when the excitation marking signals become effective, the counter stops counting, and outputs transfers a counting result to the comparator, the comparator outputs adjusting marking signals for calculating the next adjustment stage to a dichotomy module according to the relation between the counting result and a given threshold value range. In the dichotomy computing module, the next adjustment stage is calculated, and the corresponding adjustment stage is output to be configured and applied in a delay adjustment block of the PUF. Then under the adjustment stage, excitations are input to the PUF again to conduct the next round of adjustment till a counting result is in a threshold value range in the comparator, and then the comparator outputs adjustment stage number marking signals. According to the wiring delay deviation fast calibration method of the arbitration-type PUF based on the FPGA, time consumed in the adjusting process of the PUF can be effectively shortened.

Description

technical field [0001] The present invention relates to hardware security and the application field of FPGA. By inputting a suitable adjustment stage into the PUF circuit to compensate for the asymmetric delay of the wiring of the two signal channels of the FPGA-based arbitration type PUF, the arbiter PUF has better randomness and Unpredictability, thereby improving the security of PUF. In addition, the tuning of the FPGA-based arbiter PUF before it is put into use can also greatly improve the efficiency. Background technique [0002] As information security is getting more and more attention, the traditional method of storing confidential information in non-volatile memory is also facing many challenges. Storing confidential information in non-volatile memory such as fuses or EEPROM , in most cases, in order to improve security, additional protection circuits are required to be arranged around the memory, which not only increases the cost but also increases the consumption...

AI Technical Summary

Problems solved by technology

This method often requires more measurements to find the final adjustment level, so that the search process takes a lot of time and consumes a lot of power

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