45results about How to "Simplify interface design" patented technology

A compact BCH parallel decoding circuit which supports preview search works on a finite field GF(2<13>). The parallel decoding circuit comprises a syndrome arithmetic circuit(1), a realizing circuit(2)with multiple shoots in one round for IBM wrong position multinomial iterative computation in the finite field GF(2<13>), a wrong address search circuit(3) provided with a totally combined logic pre-search module and a multifunctional configurable data interface(27)of an encoder. Compared with prior art, the decoding circuit has the advantages that the hardware is of low degree of complexity, the circuit area is compact and the decoding circuit is low in cost; data throughput is high and wrong address research is quick; the interface is simple in design and is practical and multi-functional; correcting performance can be flexibly configured according to the length of the check element and is free from the change of the code length.

The invention discloses a flush-type on-site bus protocol interface device and method, which connects instrument or equipment with PROFBUS to accomplish DP passive station communication function in the on-site PROFBUS. One end of interface mode exchanges data with 8-byte or 16-byte microprocessor as intelligent controller through two-port RAM or asynchronous serial port of TTL electrical level, which can be embedded in the circuit of intelligent instrument equipment; the other end displays standard Profibus-DP passive station interface, which communicates with other equipments through the switch-in bus of Profibus-DP passive station. The invention is fit for Profibus interface of high speed and moving control device, which brings significant social and economical benefit.

The invention discloses a DSP (digital signal processor) and FPGA (field programmable gate array) system on-line updating method, which is used for solving the problem of program online updating of a DSP and FPGA digital signal processing system. The method has the technical scheme that through a universal serial bus interface, the interconnection between a host computer and a DSP is completed; a DSP and FPGA program file to be updated is transmitted to the DSP; a Flash memory of the DSP or the FPGA is controlled to be updated by a DSP automatic updating algorithm; one group of SPI interface bus of the DSP is used for completing the hardware connection and erasing and writing of two Flashes; the bus address coding is completed through a multiplexer; the bus conflict is avoided. The program updating of the two chips of DSP and FPGA is simultaneously completed under the condition without dismounting the equipment; the interface is simple; the software and hardware design complexity is low; a simple and effective method is provided for the online updating of the digital signal processing system.

The invention discloses a treatment device for business interface, which comprises: a physical interface board to treat the business data between communication device and external network, and a transmission protocol treatment board connected to former board by a back board to treat the business data treated by former board according to its transmission protocol and obtain need business data or package the business data to be transmitted according to its transmission protocol to transmit to external network by former board. This invention just needs to exploit again the opposite software when protocol changes to meet market request for diversity and exploit speed.

The on-chip system includes several functional modules connected with internal bus including two independent transmission channels, including one control/state channel for transmitting control/state information and one data channel for transmitting other data except control/state information. Each of the control/state channel and the data channel has separate data bus, address bus and control bus. The kernel of the present invention is to design on-chip system bus in the strategy of separate control/state channel and data channel, which have different topologic structures and communication protocols. The present invention has greatly simplified interface design of functional modules inside the system and increased total system communication bandwidth, and is especially suitable for on-chip system design with compact data interaction.

The invention discloses a digital-analog mixed signal processing system for imprecise computation, comprising an input module used for decomposing A B-bit digital input signals into A*B single-bit high- and low-level signals and sending the high- and low-level signals to a signal processing module as analog input signals, the signal processing module used for calculating the analog input signals to obtain C analog output signals and sending the analog output signals to an output module, and the output module used for converting the analog output signals into D high- and low-level signals and outputting the D high- and low-level signals as E F-bit digital signals, wherein D, E and F are natural numbers, and D=E*F. The digital-analog mixed signal processing system for imprecise computation has the advantages as follows: the area and power consumption of a computing system on a conversion interface are reduced effectively, and interface design is greatly simplified; and the area is reduced by more than 50%, the energy consumption is reduced by more than 60%, and the application space of the system of the type is significantly improved.

The invention relates to a security energy efficiency monitoring terminal based on a tamper-proof technology and a monitoring method of the security energy efficiency monitoring terminal, and belongs to the field of energy efficiency monitoring and management. According to the monitoring method, due to three steps of initialization, data acquisition and verification, the accuracy of energy efficiency data acquisition is guaranteed; the monitoring terminal performs CRC calculation, compares whether a CRC calculation result is matched with an initial verification value to judge whether data are maliciously tampered, so as to guarantee the security of energy efficiency data. By the adoption of a dynamic tamper-proof technology, CRC calculation verification is conducted regularly, and the result is submitted for system networking verification. Once a program is found to be tampered, a user calls the police immediately and ends the operation of the terminal. The security energy efficiency monitoring terminal can be effectively prevented from being illegally tampered when guaranteeing the accuracy and the instantaneity of the energy efficiency data. The shortcoming of low information security of the conventional monitoring terminal is overcome.

The invention provides a non-volatile random access memory (100) and an operation method thereof. The non-volatile random access memory (100) comprises a memory cell array (110) composed of multiple memory cell blocks (111), and a peripheral circuit connected to the memory cell array (110). The peripheral circuit comprises an address decoding circuit (120) for selecting the corresponding memory cell block according to address input information, a block operation-mode information register (130) for storing operation mode information of all the memory cell blocks (111) and carrying out re-writing under the action of a control signal (160), a writing driving circuit (140) for outputting a writing operation mode to the memory cell array (110) according to the operation mode information stored in the block operation-mode information register (130), and a reading circuit (150) for outputting a reading operation mode to the memory cell array (110) according to the operation mode information stored in the block operation-mode information register (130). The non-volatile random access memory is compatible with two phase change memories having different operation modes, simplifies an interface design, saves a design area, reduces power consumption and improves a speed.

The invention relates to a data transmitter in low-speed chain circuit and relative method. Wherein, said device comprises a low-speed chain circuit interface frame, a service processing frame, and a DDF support; said method comprises: the service data of service processing frame via high-speed chain circuit is transmitted to the low-speed chain circuit interface frame; the low-speed chain circuit interface frame processes said bus data to be transmitted to the DDF support via low-speed chain circuit. With said invention, the interface design of service processing frame can be simplified to improve the reliability of telecommunication equipment.

The invention provides a high-voltage module for a power electronic traction transformer, and the high-voltage module comprises: an insulating housing, wherein the upper, lower, left and right surfaces of the insulating housing are all closed, at least one part of the rear surface is an open surface, and the outer side edges of the front surface and the rear surface are respectively provided witha concentric-square-shaped groove structure; an internal frequency conversion machine core, wherein the internal frequency conversion machine core and the insulating shell are of a nested structure, and the internal frequency conversion module at least comprises a water-cooling heat dissipation assembly, an IGBT assembly, a busbar, a driving assembly, a direct-current capacitor, a control part anda water-electricity integrated rapid plug-pull connector, the water-electricity integrated rapid plug-pull connector is led out from the rear surface, the water-cooling heat dissipation assembly is located in the middle of the high-voltage module and divides high-voltage module into a left area and a right area, cascade side high-voltage IGBTs and inversion side high-voltage IGBTs in the IGBT assembly are arranged on the two sides of the water-cooling heat dissipation assembly respectively, and the IGBT assembly, the busbar and the IGBT driving assembly are sequentially arranged outwards fromthe left side to the right side of the water-cooling heat dissipation assembly.

The invention discloses an integrative information interaction method for intelligent power distribution and utilization. Data information of various types is collected to form an information class 1, which is sent to an intelligent power distribution and utilization unified supporting platform. Information in the information class 1 is analyzed and verified and is converted to another format by the intelligent power distribution and utilization unified supporting platform, so as to form an information class 2 which is sent to intelligent power distribution and utilization business application systems. Information that is needed is extracted from the information class 2 and is utilized to form control decision information. The control decision information formed by all the business application systems is sent, as an information class 3, to the intelligent power distribution and utilization unified supporting platform. Information in the information class 3 is analyzed and classified in order to form, in accordance with the classification, an information class 4 which is sent to intelligent power distribution and utilization information acquisition and control terminals. Information that is needed is extracted from the information class 4 by each terminal and is utilized. The invention realizes information interaction and compatibility of different business application systems.

The invention discloses a wireless communication signal relay system. The system is characterized by comprising a shell, a power input terminal, a relay output terminal, an indicator light, a radio frequency single-chip microcomputer module, a power module, a signal relay module, and a remote control center. The power input terminal is used for being connected with a direct current power supply. A common terminal pin, a normally open terminal pin and a normally closed terminal pin of the relay output terminal are used for being connected with loads. The system has the advantages that on or off of the signal relay is controlled through wireless packets monitored and the current state of the signal relay or power consumption of the loads is fed back to the remote control center in a wireless manner.

The invention discloses a wireless signal relay, which is characterized by comprising a shell, a power input terminal, a relay output terminal, an indicating lamp, a radio frequency singlechip module, a power module and a signal relay module, wherein the power input terminal of the wireless signal relay is connected with a direct current power supply; and a common end pin, a normally open end pin and a normally closed end pin of the relay output terminal are connected with a load. The wireless signal relay can control switch-on and switch-off of the signal relay according to a monitored wireless packet and wirelessly feed back the current state of the signal relay or the power consumption of the load to a remote control center.

The invention discloses a high-speed SM4 cryptographic algorithm circuit suitable for mobile equipment, and belongs to the field of digital circuits. The high-speed SM4 cryptographic algorithm circuit comprises a round key generation module, an RAM module, a data selector module and an encryption/decryption operation module. The round key generation module and the encryption/decryption operation module both adopt a two-degree expansion structure, iteration steps are basically consistent, each round of calculation generates two rounds of results, and the total iteration round can be reduced by half. In addition, the circuit is optimized on the basis of a two-degree expansion structure, the number of stages of the gate circuit is reduced, and the operation speed is effectively increased. According to the SM4 cryptographic algorithm, the round key generation circuit module and the encryption/decryption operation circuit module adopt a parallel architecture to realize the SM4 cryptographic algorithm, the working speed is high, the calculation time is short, the total processing round of the design circuit is a constant, and side channel attacks can be effectively resisted.