10 results about "Intra-frame" patented technology

Systems and methods are disclosed for modifying the encoding of a video in an ultra low-latency environment in response to a dropped or corrupted packet. A video source encodes the video using slice or tile encoding. Slice encoding divides each frame of the video into slices which are independently encoded. Each frame in a slice stream is either intra-coded or predictively encoded. Each slice or tile in an Intra frame, Predicted frame or bi-directional frame may be independently encoded as an Intra slice or tile, a predicted slice or tile or a Bi-directional slice or tile. Slices or tiles of each frame are multiplexed into data packets for transmission. In response to feedback indicating that a data packet was corrupted, is late or dropped, the video source determines what data was in the transmission data packet and modifies encoding of a subsequent slice or tile in the slice or tile stream to be intra-coded.

Example systems, apparatus, articles of manufacture, and methods to implement hardware-accelerated intra frame encoding are disclosed. Example hardware-accelerated intra frame video encoders disclosed herein are VC3 compliant. Some example video encoders disclosed herein quantize alternating current (AC) coefficients of a macroblock of an input image frame using a small set of anchor quantization scale factors (QSFs), and interpolate between the resulting bit counts for the first anchor QSFs to determine an estimated QSF meets a target bit budget. Some example video encoders disclosed herein perform bit coding with a round-robin packing strategy that distributes the packing of encoded symbols among macroblocks and discards excess symbols to avoid exceeding the specified frame size. Some example video encoders disclosed herein are configurable via control circuitry and / or a driver that selects target bit budgets, anchor QSFs, encoding modes, etc., thereby enabling single or multi pass operation and adjustable performance versus quality trade-offs.

A mesh decoding device 200 includes: an intra decoding unit 202B that decodes coordinates of a vertex and connectivity information in an intra frame from a bit stream of the intra frame; and an inter decoding unit 202E that decodes coordinates of a decoding target vertex by adding a motion vector decoded from a bit stream of an inter frame and coordinates of a vertex corresponding to the decoding target vertex in a reference frame. the number of submeshes can be different in each of the intra frames, and the number of submeshes can be different in each of the inter frames.

A mesh decoding device 200 includes: an intra decoding unit 202B that decodes a base mesh from a bit stream of an intra frame; and an inter decoding unit 202E that decodes a motion vector from a bit stream of an inter frame, adds the motion vector to a base mesh of a reference frame, and decodes the base mesh, wherein the intra decoding unit 202B or the inter decoding unit 202E includes a duplicate vertex search unit 202E6 that acquires information related to a duplicate vertex of a vertex to be decoded from a decoded vertex.

Example systems, apparatus, articles of manufacture, and methods to implement hardware-accelerated intra frame encoding are disclosed. Example hardware-accelerated intra frame video encoders disclosed herein are VC3 compliant. Some example video encoders disclosed herein quantize alternating current (AC) coefficients of a macroblock of an input image frame using a small set of anchor quantization scale factors (QSFs), and interpolate between the resulting bit counts for the first anchor QSFs to determine an estimated QSF meets a target bit budget. Some example video encoders disclosed herein perform bit coding with a round-robin packing strategy that distributes the packing of encoded symbols among macroblocks and discards excess symbols to avoid exceeding the specified frame size. Some example video encoders disclosed herein are configurable via control circuitry and / or a driver that selects target bit budgets, anchor QSFs, encoding modes, etc., thereby enabling single or multi pass operation and adjustable performance versus quality trade-offs.

Systems and methods are disclosed for modifying the encoding of a video in an ultra low-latency environment in response to a dropped or corrupted packet. A video source encodes the video using slice or tile encoding. Slice encoding divides each frame of the video into slices which are independently encoded. Each slice or tile in an intra frame, predicted frame, or bi-directional frame may be independently encoded as an Intra slice or tile, a predicted slice or tile or a Bi-directional slice or tile. Slices or tiles of each frame are multiplexed into data packets for transmission. In response to feedback indicating that a data packet was corrupted, late, or dropped, the video source determines what data was in the transmission data packet and modifies encoding of a subsequent slice or tile in the slice or tile stream to be intra-coded.

Various embodiments provide methods, apparatuses, and computer program products. An example apparatus includes at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: selecting a first frame to be a random access point (RAP) frame; setting an open bitstream unit (OBU) RAP flag equal to a first value for OBUs in a temporal unit of the first frame; setting a frame type as a key frame in a frame header of the first frame; and coding the first frame as an intra frame.

A mesh decoding device 200 includes: an intra decoding unit 202B that decodes coordinates of a vertex and connectivity information in an intra frame from a bit stream of the intra frame; and an inter decoding unit 202E that decodes coordinates of a decoding target vertex by adding a motion vector decoded from a bit stream of an inter frame and coordinates of a vertex corresponding to the decoding target vertex in a reference frame. The intra decoding unit 202B and the inter decoding unit 202E include a duplicate vertex search unit 202E6 that acquires the number of vertices having a duplicate vertex from decoded vertices, and the intra decoding unit 202B and the inter decoding unit 202E decode a control signal indicating the number of vertices having the duplicate vertex from a bit stream.

A method of signing prediction-coded video data comprises: obtaining a coded video sequence comprising a set of frames including at least one intra frame having independently decodable image data, and at least one inter frame, containing image data decodable by reference to another frame; generating a group hash of the coded video sequence by hashing the image data of the coded video sequence; generating a plurality of individual hashes of frame subsets including at least one frame by hashing the image data derived from each of the frame subsets, reducing the length of each of the individual hashes to a length shorter than a total length of the group hash, generating a digital signature by encrypting at least the group hash and the individual hashes with reduced lengths; providing the group hash and the reduced length individual hashes together with the digital signature and the coded video sequence.

An intra frame prediction method and apparatus based on interpolation filtering, a video encoding method and apparatus, a video decoding method and apparatus, and a system. The intra prediction method based on interpolation filtering comprises: during the intra prediction process of video encoding and decoding, determining, according to a filtering window of the current block and reconstruction values of pixel points in a reconstruction region adjacent to the current block, a filtering coefficient which is used when interpolation filtering is performed on the current block; and performing point-by-point prediction on the pixel points in the current block according to the filtering window and the filtering coefficient, so as to obtain a predicted block of the current block. In the embodiments of the present disclosure, a predicted block of the current block is obtained using the current block and the spatial redundancy of a reconstruction region adjacent thereto, such that the encoding performance can be improved.