Temperature-insensitive clock buffer and H-shaped clock tree circuit

Abstract

The invention provides a temperature-insensitive clock buffer (TICB) and an H-shaped clock tree circuit. The TICB comprises a first phase inverter, a second phase inverter, a first NMOS tube and a second NMOS tube, wherein the output end of the first phase inverter is connected with the input end of the second phase inverter; the input end of the first phase inverter is used as the input end of the TICB, and the output end of the second phase inverter is used as the output end of the TICB; the drain of the first NMOS tube is connected with the input end of the first phase inverter, the grid of the first NMOS tube is connected with the output end of the first phase inverter, and the source of the first NMOS tube is connected with a low level; and the drain of the second NMOS tube is connected with the input end of the second phase inverter, the grid of the second NMOS tube is connected with the output end of the second phase inverter, and the source of the second NMOS tube is connected with the low level. The H-shaped clock tree circuit comprises a plurality of TICBs. The technical scheme of the invention can resist temperature deviation and reduce clock skew caused by non-uniform temperature distribution, thereby ensuring the performance of an integrated circuit.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a temperature-insensitive clock buffer and an H-type clock tree circuit. Background technique [0002] According to ITRS2009 data, the power consumption density of high-performance processors has reached 120W / cm 2 , such a high power density causes the chip temperature to be too high. At the same time, the use of a large number of on-chip memories, multiple power domains, dynamic voltage frequency scaling (DVFS), clock gating and other technologies make the temperature distribution in the chip very uneven. In some processors, the temperature difference can even reach 77 degrees Celsius. [0003] Since resistances of CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) transistors and metal interconnection wires are sensitive to temperature, changes in temperature will affect circuit delays. The uneven temperature distribution in the chip will cause th...

AI Technical Summary

Problems solved by technology

However, for a design with useful clock skew (useful skew) technology applied, the delay of the clock signal from the clock source to the flip-flop is not required to be uniform, so the traditional clock network cannot solve the clock skew problem caused by temperature.

At the same time, the clock network design method needs to consume more precious routing resources

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