Built-in self-test structure and method for on-chip network resource node storage device

Abstract

The invention discloses a built-in self-test structure and method for an on-chip network resource node storage device. The built-in self-test structure comprises a built-in self-test (BIST) controller arranged on a field programmable gate array (FPGA) chip, a resource network interface and a BIST interface which are embedded into corresponding routers, a test pattern generator and a test response analyzer, wherein the BIST controller is connected with external test equipment through an external interface. The built-in self-test method comprises the following steps that: the external test equipment sends an instruction start test program to the BIST controller; the BIST controller sends an enabling signal and a state selection signal to each test module according to a March C+ test algorithm program, performs read-write operation on each address of a static random access memory (SRAM) under each test state, and stops sending the signals if failures are found out. A test result is sent to the external test equipment. According to the built-in self-test structure and method, the test time is reduced by 50 percent; a routing network of a network operation center (NoC) is reused as a test data route; data transmission is reliable and safe; a chip area is low in expense; the failure coverage rate is high.

Description

technical field [0001] The invention relates to the technical field of Network-on-chip (NoC) testing, in particular to a built-in self-testing structure and a self-testing method of a network-on-chip (NoC) resource node memory. Background technique [0002] With the advancement of semiconductor technology and the continuous improvement of SoC (System-on-chip, SoC) technology, SoC technology has become the main design technology of integrated circuits in this century. However, its design method and architecture have exposed limitations, especially when the number of IP cores included in the SoC increases to tens of thousands, the existing SoC technology based on the bus structure is facing challenges in Huge challenges in terms of performance, power consumption, latency, and reliability. The problems that arise are specifically manifested in the following three aspects: [0003] 1. The address space of the bus structure is limited, which leads to the problem of poor scalabi...

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Problems solved by technology

[0003] 1. The address space of the bus structure is limited, which leads to the problem of poor scalability

[0004] 2. The bus structure adopts time-sharing communication, which leads to low communication efficiency. Multiple users on the bus share bus resources at the same time. The number of users communicating on a bus at a certain time cannot exceed one pair

[0005] 3. The power consumption and area of ​​the bus structure due to the use of a global synchronous communication mechanism

[0014] At present, there have been a large number of built-in self-test designs for SoC memories with bus structures, but there have been no reports on the use of built-in self-test methods for memories in NoC systems.

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