Device and method for testing system-on-chip chip with multiple isomorphic IP cores

A system-on-chip and testing device technology, applied in measurement devices, digital circuit testing, electronic circuit testing, etc., can solve problems such as inconsistent running states, occupying shift time, and unintuitive processing, reducing vector debugging time, The effect of small area overhead and test cost saving

Active Publication Date: 2010-07-28
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although this method has good scalability and flexibility, because the running state of each core is inconsistent, additional commands are required to control the state of each core, making the control complicated. In addition, the vector conversion and the X-bit The processing is not intuitive, and the processing of X bits takes extra shift time

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  • Device and method for testing system-on-chip chip with multiple isomorphic IP cores
  • Device and method for testing system-on-chip chip with multiple isomorphic IP cores
  • Device and method for testing system-on-chip chip with multiple isomorphic IP cores

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Embodiment Construction

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, a system-on-chip (SOC) chip testing device and method with an isomorphic IP core of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention rather than limit the present invention.

[0040] The solution provided by the invention utilizes the characteristics of the isomorphic IP core, and uses limited IO resources and simple control logic to achieve the purpose of reducing the amount of test data and test cost.

[0041] The system-on-chip (SOC) chip testing device with isomorphic IP core of the embodiment of the present invention, as figure 1 As shown, in a SoC chip with multiple isomorphic IP cores 6, including a controller 1, and a plurality of conditional comparators 2 corresponding to ea...

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Abstract

The invention discloses a device and a method for testing a system-on-chip chip with a plurality of isomorphic IP cores. The device comprises a controller and a condition comparator, wherein the controller is provided with a plurality of control signal interfaces connected to each corresponding isomorphic IP core and is used for inputting a test control signal to each isomorphic IP core, controlling the test on one or more isomorphic IP cores, broadcasting the same test excitation data to the IP cores and simultaneously controlling the output of a test response of a certain IP core; the test response serves as a reference test response and is compared with the test responses of other IP cores; and the condition comparator is used for comparing the test response of a corresponding IP core with the reference test response and processing the comparison result to produce a one-bit error identification signal for identifying whether the comparison is accordant.

Description

technical field [0001] The present invention relates to the field of integrated circuit testing, in particular to the testing of a system-on-chip (SOC chip) containing an isomorphic IP core, and in particular to a device and method for applying scanning test stimulus to a multi-core processor that needs to reduce testing overhead and testing cost. As well as test response on-chip comparison apparatus and methods. Background technique [0002] Today, the vast majority of integrated circuits are designed with scans and tested with scan chains. This structural test method for testing through scan chains can greatly reduce the complexity of automatic test pattern generation (Automatic Test Pattern Genaration, ATPG), and greatly improve the test coverage of faults. [0003] The basic steps of scan testing through the scan chain are: 1) apply the test vector to the chip along the scan chain through the scan input port; 2) switch to the functional state, and run for one or several...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317G01R31/3183
Inventor 刘慧齐子初胡伟武
Owner LOONGSON TECH CORP
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