42results about How to "Guaranteed equivalence" patented technology

The invention discloses a device and a method for testing a system-on-chip chip with a plurality of isomorphic IP cores. The device comprises a controller and a condition comparator, wherein the controller is provided with a plurality of control signal interfaces connected to each corresponding isomorphic IP core and is used for inputting a test control signal to each isomorphic IP core, controlling the test on one or more isomorphic IP cores, broadcasting the same test excitation data to the IP cores and simultaneously controlling the output of a test response of a certain IP core; the test response serves as a reference test response and is compared with the test responses of other IP cores; and the condition comparator is used for comparing the test response of a corresponding IP core with the reference test response and processing the comparison result to produce a one-bit error identification signal for identifying whether the comparison is accordant.

The invention discloses an automatic production line system for coating and maintaining buoys and an application method thereof. The system comprises a hanging and conveying device, a blasting cleaning plant, a shot blasting cleaning plant and a drying unit; all the devices are provided with hanging type loading workpieces; the hanging type loading workpieces are used for realizing ascending and descending, walking and autorotation of the buoys in the process of cleaning the blasting and shot blasting, spraying painting and drying.The application method comprises: a. a trolley is moved to a ring-shaped rail to hoist buoys; b. the buoys enter a cleaning room to carry out blasting and shot blasting; c. the buoys enter a spray room to be painted; d. the buoys enter a drying room to be dried; e. the buoys once again enter the spray room to be painted once again; f. the buoys are dried once again. In the invention, the workpieces are loaded in a hanging manner, the lifting appliances can ascend and descend, walk and automatically rotate. Blasting and shot blasting cleaning, paint spraying, three-station drying are completed respectively to form an automatic coating processing production line; and in addition, program control is realized and a high degree of automation is enjoyed.

The invention discloses a method for constructing pore throat sections of a rock pore network model by considering concavity and convexity in the technical field of image processing. The method comprises main steps of scanning a real rock core based on a CT technology and performing three-dimensional reconstruction; performing pore throat segmentation on the three-dimensional rock core, performing numbering and sorting on all pore throats, and making statistics on pore throat geometric parameter information; obtaining a relationship between a maximum inner angle of a quadrangle and a shape factor by utilizing a numerical experiment; determining the maximum inner angle of the quadrangle according to the concavity and convexity and the shape factor; making a diagonal line from a vertex of the angle, dividing the maximum inner angle into two parts, and determining the length of the diagonal line; establishing a section nonlinear feature equation and calculating the side length of the quadrangle with a Newton iteration method; and checking whether the feature equation has a positive solution and conforms to physical significance or not, and if not, performing reconstruction until all the pore throat sections are constructed. According to the method, the concavity and convexity of the cross section and the equivalency of the hydraulic radius of a porous medium are fully considered, so that the accuracy of representing the real porous medium by the pore network model is improved and a seepage parameter of the porous medium can be accurately predicted.

The invention provides a method for eliminating internal nodes of a metal-oxide-semiconductor field effect transistor (MOSFET) used in rapid circuit simulation. The method comprises the following steps of: making a 4-node MOSFET model which does not comprise any internal node equivalent to a 6-node MOSFET model which comprises internal nodes in a circuit simulation process; solving the voltages of two internal nodes of the MOSFET by an analytic method; calculating the change of an internal node voltage along with an external node voltage; and finally obtaining a transient conductance relation among external nodes of all apparatuses used in matrix calculation. The method has the advantages of ensuring circuit simulation accuracy by considering the effect of MOSFET parasitic resistance on an electrical property, eliminating the internal nodes of the MOSFET, reducing a circuit solving matrix, reducing matrix solving time and increasing circuit simulation speed.

The invention relates to an air-uniformizing and thermoforming baking oven which comprises an oven body, a heater, a conveying chain plate, a suction hood, a reflux pipeline and a draught fan, wherein the bottom of the oven body is provided with an air uniformizing device which is composed of an air inlet pipe and an air uniformizing chamber; one end of the air inlet pipe is connected with the draught fan, and the other end of the air inlet pipe is connected with the air uniformizing chamber; the air uniformizing chamber comprises an end plate, two side plates and a bottom plate; the end plate is provided with an air inlet; the air inlet pipe is connected with the air inlet; multiple inclined air deflectors are arranged in the air uniformizing chamber; flow channels are respectively formed between the multiple air deflectors and the bottom plate and are connected with the air inlet; one ends of the multiple air deflectors are respectively connected with the end plate, and the other ends of the air deflectors are parallel to one another and are respectively provided with multiple air outlets. The air-uniformizing and thermoforming baking oven can be used for not only ensuring that air absorbs the same heat in the heater and thus the service life of the heater is prolonged, but also ensuring that fibers absorb the same quantity of heat and thus the fiber thermoforming degree is stabilized, and further ensuring the product quality consistency.

The invention belongs to the technical field of traditional Chinese medicine, and relates to a herba violae extract. The extract is prepared by the following methods: ethanol extraction, decompression concentration, purification with macroporous adsorption resin, concentration, drying and the like. Compared with the prior art, the herba violae extract disclosed by the invention greatly improves the contents of total coumarin and esculetin, wherein the total coumarin content is improved to be above 40% from 1.7% in medicinal materials and the esculetin content is improved to be above 15% from 0.5%. Upon pharmacological tests, T1 of the herba violae extract on herpes simplex viruses is 8, showing that the extract is relatively strong in effect on inhibiting the herpes simplex viruses.

The invention relates to an on-off terminal short-circuit fault testing of a 800kV and a 1100kV ultra-high/extremely-high voltage AC circuit breaker, in particular to an on-off terminal short-circuit fault testing loop of an ultra-high/extremely-high voltage circuit breaker. The on-off terminal short-circuit fault testing loop comprises a test main electrical power source and a test circuit breaker. The invention is characterized in that the on-off terminal short-circuit fault testing loop also comprises a first auxiliary circuit breaker, a second auxiliary circuit breaker, a first voltage source and a second voltage source, wherein, the first auxiliary circuit breaker is connected between the high-voltage end of the test main power source and one terminal of the test circuit breaker in series, the second auxiliary circuit breaker is connected between the low-voltage end of the test main power source and the other terminal of the test circuit breaker in series, the first voltage source is connected with the test circuit breaker in parallel, and the second voltage source is connected with the second auxiliary circuit breaker in parallel.

A digital frequency selection measuring system capable of resisting one hundred thousand times of interference relates to the technical field of measurement. A voltage measurement function front-end circuit of the digital frequency selection measuring system comprises a voltage measuring terminal, an automatic range switching unit, a filter circuit unit and an isolation and amplification unit, a CPU (central processing unit) transmits a signal to control the automatic range switching unit to automatically switch ranges, the automatic range switching unit is connected to the filter circuit unit, the filter circuit unit is connected to the isolation and amplification unit, and output of the isolation and amplification unit is connected to the CPU. A current signal of a current measuring terminal is inputted to an automatic range switching unit, the CPU transmits a signal to control the automatic range switching unit to automatically switch ranges, the automatic range switching unit is connected to a filter unit, the filter unit is connected to an operational amplification unit, the operational amplification unit is connected to the CPU, and the CPU carries out analytic processing. The digital frequency selection measuring system can realize frequency selection measurement with resistance to one hundred thousand times of interference on the basis of +/-1Hz, and has important application in the field of electric measurement, particularly in the field of test of electric systems under the background with high interference.

The invention relates to a complex RCS data interpolation method based on compressed sensing, and belongs to the technical field of comprehensive experimental testing. A specific implementation mannerof the method comprises: constructing a complex domain reconstruction model according to the RCS measurement data; solving the complex domain reconstruction model, acquiring a sparse distribution ofthe RCS data; and reconstructing the target frequency domain data based on the sparse distribution to implement complex RCS data interpolation. Compared with the conventional method for simply diagonalizing the complex matrix, the invention has rapid processing speed and high precision without reducing or increasing the original constraint range, and is capable of effectively shortening the measurement time to improve the RCS measurement efficiency.

The invention discloses a reduced scale equivalent physical experiment method for an electric transmission line, and belongs to the technical field of high voltage overhead power transmission. The method comprises the steps that firstly, an electric transmission line reduced scale equivalent physical experiment is set in an ultra-long distance and large-capacity half-wavelength (3,000 km) power transmission mode; secondly, three reduced scale schemes of an equal proportion reduced scale, an equal electric conductivity reduced scale and an equal radius reduced scale are provided according to the relation among the reduced scale multiple, frequency and half wavelength of the electric transmission line reduced scale equivalent physical experiment; the equal electric conductivity reduced scale scheme is selected preferentially through calculation and comparison. Compared with an existing method for researching electric transmission line transmission characteristics, the equivalence before and after the electric transmission line reduced scale can be ensured, and a real electric transmission line is accurately simulated. The method has the advantages that a circuit is easy to construct and the equivalence is good, and has the good application prospect on the occasion that the electric transmission line needs to be used for performing an experiment.

The invention discloses a power semiconductor device for testing a gate pole current. The device comprises a power semiconductor chip and a tube shell. The power semiconductor chip comprises a plurality of first insulating layers and a plurality of sub gate pole annular electrodes; the first insulating layers divide a gate pole common metal region of the power semiconductor chip into a plurality of sub gate pole common metal regions, and the plurality of sub gate pole common metal regions are connected with the plurality of sub gate pole annular electrodes in a one-to-one correspondence manner; the tube shell comprises a plurality of sub gate pole contact rings and a plurality of sub-insulating seat inner metal rings, and the sub gate pole contact rings and the sub insulating seat inner metal rings are arranged with the plurality of sub gate pole annular electrodes in a one-to-one correspondence manner; and a plurality of square grooves are formed in a cathode copper block on the outerside of a tube shell gate pole groove, and gate pole leading-out strips are arranged in the square grooves so as to lead out gate pole currents on the corresponding sub gate pole annular electrodes respectively. The power semiconductor device can effectively lead out gate pole currents of different cathode strip-shaped areas in the power semiconductor chip so as to achieve a purpose of measurement.

The invention discloses a composite insulator umbrella skirt unevenness aging test platform and a using method thereof. An umbrella-shaped support skeleton with the same shape and the same size as thecomposite insulator umbrella skirt is constructed, and the umbrella-shaped support skeleton is mounted on a vertical column to form a test platform; samples are evenly mounted on the outer surface ofthe umbrella-shaped support skeleton; the test platform provided with the samples is placed in an outdoor environment for aging test, a direction indicator is used to indicate the mounting directionof the test platform, and through an environmental sensor, environmental data are recorded; after a test period is reached, an umbrella-shaped support skeleton drawing is printed, the position and thedirection of a direction arrow are marked on the printed drawing on the spot, the samples are removed from the umbrella-shaped support skeleton one by one and are numbered, a sample number is filledat a corresponding position on the drawing, the samples on each layer of the umbrella-shaped support skeleton need to be filled in a drawing, and a layer number of the umbrella-shaped support skeletoncounting from top to bottom is marked closely near the drawing; and the taken sample is subjected to subsequent aging performance analysis and detection.

The invention relates to a partial-node big data service system, and the system comprises a speed recognition device which is disposed in a helmet of a player who carries out a steel frame snowmobile project, and is used for measuring the current traveling speed of the helmet; the signal conversion device is used for sending a signal for requesting to capture a field super-definition picture when the received current advancing speed exceeds or is equal to the minimum competition speed; and the racing track speed reduction equipment is used for executing inclination processing on a racing track in front of the current position of the helmet after receiving the speed reduction request instruction so as to execute speed reduction operation on the upcoming steel frame snowmobile. The invention further relates to a partial node big data service method. According to the invention, when it is detected that a player of a steel frame snowmobile item is in a top speed state at present, whether the player is seriously lost in posture or not is judged based on the left-right symmetry degree of the ice surface of the front racing track, and corresponding racing track deceleration processing and vehicle body deceleration processing are executed when the player is judged to be seriously lost in posture, so that the emergency capability of competition management is improved.

The invention provides an angle splicing card and a card board thereof. The angle splicing card at least comprises one group of twelve triangular sub cards, wherein identifying parts are respectively arranged in center areas in a vortex angle, two base angles and a triangular surface of at least one card surface of the sub cards; any two triangular surfaces with the identifying parts are different in the twelve sub cards; various identifying parts on the same triangular surface are different; at least two sub cards are arranged on the same triangular surface; and when vertex angles and one base angle of the sub cards are spliced together, the identifying parts on two base angles can be spliced into a complete card sign. The card board is square and is formed by splicing the sub cards; andevery four sub cards are spliced into a minimum square matrix. In the invention, each sub card can provide at least four single cards; and with a special triangular splicing structure, multiple game methods for splicing the card sings, distinguishing the card colors, comparing the sizes of the card signs, and the like can be realized. Therefore, compared with the traditional card games, the anglesplicing card has stronger interestingness and more remarkable function of improving intellectual development.

The invention provides a model training method and device, and relates to the technical field of big data, machine learning and the like. According to the specific implementation scheme, a training sample is obtained according to an auxiliary sample and a target sample which are obtained in advance; a preset weight rule is adopted to generate training weights of the training samples, and the weight rule is used for enabling the weight proportions of the auxiliary samples and the target samples to be the same; executing the following training steps: inputting a training sample and a training weight into a base learning device to obtain the output of the base learning device; and based on the output of the base learner, adopting a migration operator to adjust the training weight until a training stop condition is met, and obtaining a target model. According to the embodiment, the modeling efficiency is improved.

The invention relates to the technical field of measurement, in particular to a method and a system for testing inter-phase coupling capacitance of a lightning arrester based on a different-frequencymethod. By adopting a different-frequency measurement method and matching a frequency-selective measurement device with high accuracy and strong interference resistance, accurate measurement of the inter-phase coupling capacitance of the lightning arrester can be realized; through the method and the system, disclosed by the invention, the purpose of simple and safe testing can be achieved, and themethod and the system are expected to be a solution for safely, simply, efficiently and accurately measuring the inter-phase coupling capacitance of the lightning arrester.

A signal processor for compressing signal data, including a function shapes generator for receiving as input time and frequency scale parameters, and for generating as output a plurality of shape parameters for a corresponding plurality of localized functions, wherein the shape parameters govern the centers and spreads of the localized functions, a matrix generator for receiving as input the plurality of shape parameters and a sequence of sampling times, and for generating as output a matrix whose elements are the values of the localized functions at the sampling times, a signal transformer for receiving as input an original signal and the matrix generated by the matrix generator, and for generating as output a transformed signal by applying the matrix to the original signal, and a signal compressor for receiving as input the transformed signal, and for generating as output a compressed representation of the transformed signal.