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54results about How to "Save I/O resources" patented technology
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Device and method for testing system-on-chip chip with multiple isomorphic IP cores
ActiveCN101788644AReduced amount of test dataAvoid time costDigital circuit testingComputer hardwareReference test
The invention discloses a device and a method for testing a system-on-chip chip with a plurality of isomorphic IP cores. The device comprises a controller and a condition comparator, wherein the controller is provided with a plurality of control signal interfaces connected to each corresponding isomorphic IP core and is used for inputting a test control signal to each isomorphic IP core, controlling the test on one or more isomorphic IP cores, broadcasting the same test excitation data to the IP cores and simultaneously controlling the output of a test response of a certain IP core; the test response serves as a reference test response and is compared with the test responses of other IP cores; and the condition comparator is used for comparing the test response of a corresponding IP core with the reference test response and processing the comparison result to produce a one-bit error identification signal for identifying whether the comparison is accordant.
Owner:LOONGSON TECH CORP
Multimedia storage method, system and device
ActiveCN101662628ASave I/O resourcesReduce wasteTelevision system detailsColor television detailsComputer hardwareMedia server
The invention relates to multimedia storage method, system and device. The multimedia storage method comprises the following steps: acquiring a user recording program list and recording document information of the recorded multimedia contents; judging whether to accept or reject the recorded multimedia contents according to the user recording program list and the recording document information, saving necessary recording documents in the recorded multimedia contents according to the result of the judgment, and deleting unnecessary recording documents in the recorded multimedia contents. The user recording program list is used for providing time shifting service or / and review service. The technical scheme can share one recording document in a time shifting and review mode, reduce the IO resources by writing and storing with one media server, double the recording performance of the media server and also reduce the storage space waste of the recorded contents of the time shifting programs.
Owner:XFUSION DIGITAL TECH CO LTD
Multi-digit digital pipe control circuit and method thereof
The present invention discloses a multi-bit nixietube control circuit and a method thereof. The control circuit comprises a nixietube, the drive circuit of the nixietube, latch drive circuits, a microprocessor and a decoding circuit. The present invention is characterized in that an eight-bit nixietube is used as a control unit of a section or a bit; two latch circuits are respectively used for section drive and bit drive of the nixietube. The method (1) comprises: the data input terminals of section latches and bit latches are independent and separate and are connected with the data transmission permission terminals in parallel, the data transmission permission terminals are directly connected with the microprocessor or connected the microprocessor by the decoding circuit. The method (2) comprises: the data input terminals of the section latches and the bit latches are connected in parallel, and the data transmission permission terminals are independent and separate; the independent and separate data transmission permission terminals of the sections and the bits are respectively connected with the microprocessor; the data signals of the section latches and bit latches of each control unit respectively drive the corresponding nixietube by the drive circuit of the nixietube. The method solves the problem of high cost when the multi-bit nixietube is driven or a plurality of LEDs are used for imaging.
Owner:李舒
High-precision real-time clock chip
InactiveCN103226376AHigh precisionSolve electromagnetic interferenceGenerating/distributing signalsCapacitanceDigital converter
The invention discloses a high-precision real-time clock chip which comprises a clock timing module, an I2C interface module, an alarming and periodic interrupt module, a power management module and a digital temperature compensation crystal oscillator; the clock timing module comprises a second register, a minute register, an hour register, a week register, a day register, a moon register, a year register and a square wave output control register; the hour register, the day register, the moon register and the year register are connected with a combinational logic circuit; and the digital temperature compensation crystal oscillator comprises a temperature sensor, an analogue digital converter, a storage cell, a capacitor array and a crystal oscillator. The high-precision real-time clock chip provided by the invention can be repaired and adjusted within an industrial temperature range, can achieve self calibration, greatly improves the accuracy of RTC, meanwhile the problem of electromagnetic interference on macroscopic circuit wiring can be solved, and more I / O resources of the main system are saved.
Owner:SHENGZHOU HUAFENG ELECTRONICS
Configurable low-speed PAD and BMC chip possessing intelligent reconfigurable interface
ActiveCN107390575AWith pull-up resistor functionRealize multiplexingProgramme controlComputer controlElectrical resistance and conductanceLow speed
The invention relates to a configurable low-speed PAD and a BMC chip possessing an intelligent reconfigurable interface. The chip is characterized in that the chip includes an ARM; the ARM is connected to the configurable low-speed PADs, low-speed PADs and high-speed PADs; the ARM is connected to an interface control logic module; the interface control logic module is connected to the configurable low-speed PADs, the low-speed PADs and the high-speed PADs; the configurable low-speed PADs, the low-speed PADs and the high-speed PADs are connected to an BMC chip pin respectively; and there are the several configurable low-speed PADs, the several low-speed PADs and the several high-speed PADs. In the invention, the configurable low-speed PADs are designed, open drain output and normal output functions are possessed, and a pull-up resistor function under an I2C mode is possessed too. After the BMC chip is molded, the interface can be intelligently configured and great convenience is brought for a board-grade design. IO resources can be saved, and interface reuse of the BMC chip to 12C, SPI and PCIE is realized.
Owner:ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
Intelligent waste sorting collection garbage can and sorting collection method thereof
InactiveCN109264259AHigh precisionSave I/O resourcesWaste collection and transferRefuse receptaclesInductorLateral displacement
The invention relates to a garbage can, in particular to an intelligent waste sorting collection garbage can and a sorting collection method thereof. The garbage can comprises a garbage can upper boxand a garbage can lower box, a turnable garbage can cover plate is arranged on the top of the garbage can upper box, and an electronic lock is arranged on the garbage can upper box, a lateral displacement inductor is arranged on the side wall of the garbage can upper box, a mechanical induction plate is arranged at the bottom of the garbage can upper box, a resistance-strain gravity inductor is arranged on the side wall of the garbage can upper box, a bottom displacement inductor is arranged at the bottom of the lower portion of the mechanical induction plate, the mechanical induction plate isa plate capable of being opened and closed, the garbage can upper box and the garbage can lower box are communicated or cut off through opening and closing of the mechanical induction plate, and thegarbage can lower box is provided with a garbage outlet. Accordingly, by means of an intelligent sorting garbage can, mandatory waste sorting in a residential area is implemented, and the awareness ofactively sorting household waste is helped to be improved for people.
Owner:SICHUAN UNIV
Electric car controller integrating battery management and complete car control functions
InactiveCN104802656ASave I/O resourcesImprove reliabilitySpeed controllerVehicular energy storageComputer moduleElectric cars
The invention relates to an electric car controller integrating the battery management and complete car control functions. The controller mainly comprises a microprocessor module, a power supply module, an analogue input module, a temperature acquiring module, a switching quantity input module, a switching quantity output module, a CAN interface module, a balancing module and a voltage acquiring module, wherein the analogue input module and the temperature acquiring module are respectively used for connecting signals to the microprocessor module; the power module is respectively connected with the switching quantity input module, the switching quantity output module, the CAN interface module, the balancing module, the voltage acquiring module; the switching quantity input module, the switching quantity output module, the CAN interface module, the balancing module and the voltage acquiring module are respectively connected with the microprocessor module through a first isolating circuits. According to the controller, the car can be controlled to normally run according to the battery management and the complete control; the fault can be determined; the charge and discharge states can be obtained; the charge can be balanced to ensure the consistency of batteries.
Owner:SHAANXI AUTOMOBILE GROUP
AES decryption and decryption method and circuit for FPGA with limited IO resource
ActiveCN105721139AIncrease profitSave I/O resourcesEncryption apparatus with shift registers/memoriesComputer hardwareAdvanced Encryption Standard
The invention relates to an AES (Advanced Encryption Standard) decryption and decryption method for FPGA with limited IO resource. The AES decryption and decryption method includes the following steps: 1) a data processing module receives the input data and buffers the data into an input buffer cache; 2) an FPGA chip sends the data input in the buffer cache to an encryption unit or a decryption unit through a control command; 3) the FPGA chip sends the encrypted or decrypted data to an output buffer cache through the control command; 4) the FPGA chip reads the data in the output buffer cache through the control command; and 5) a system state signal is sent through a state manager and a command module. Compared with the prior art, the AES decryption and decryption method and circuit for FPGA with limited IO resource have the advantages of saving IO resource and being high in the program transportability.
Owner:上海航天智能装备有限公司
Elevator calling and registering system and elevator
The invention provides an elevator calling and registering system and an elevator. The system comprises a resistance unit, a power supply, a pull-down resistor and a registering unit; one end of the resistance unit is connected with the power supply, and the other end of the resistance unit is grounded through the pull-down resistor; the resistance unit comprises two or more resistors and button switches, all the resistors are connected with one another in series, and each resistor is connected with one button switch in parallel; each button switch corresponds to a floor, wherein the resistance value of the any one resistor does not equals to the resistance value of the other resistor; one input end of the registering unit is connected between the resistance unit and the pull-down resistor, is used for acquiring the input voltage of the pull-down resistor, and determines the elevator calling information of a user according to the acquired voltage value; and the elevator comprises at least one elevator calling and registering system. The elevator calling and registering system and the elevator have simple structures, are convenient to install and debug, use less wires and are low in cost.
Owner:HITACHI ELEVATOR CHINA
System and method for automatically allocating communication addresses for slave nodes of industrial bus
The invention discloses a system and method for automatically allocating communication addresses for slave nodes of an industrial bus. The system comprises a master node and a plurality of slave nodes, and is characterized in that the master node and each of the slave nodes are respectively connected to the industrial bus; the master node sends a first chip selection signal to each of the slave nodes, and the slave nodes acquire data on the industrial bus; the master node is used for sequentially selecting one slave node to act as a slave node to be allocated, driving the first chip selection signal corresponding to the slave node to be allocated to be at effective state, enabling a target address to act as bus data and sending the target address to the industrial bus; and the slave node to be allocated is used for acquiring data on the industrial bus when the corresponding first chip selection signal is detected to be at an effective state and setting the data to be a communication address. The invention realizes a novel mode for automatically allocating communication addresses for the slave nodes of the industrial bus, and automatic allocation of the communication addresses can be realized simply and quickly through maintaining one program.
Owner:SHANGHAI ELECTRICGROUP CORP
Contact type acoustic wave sensing device
InactiveCN108519148AReduce the impactSave I/O resourcesSubsonic/sonic/ultrasonic wave measurementUsing electrical meansMicrocomputerMicrocontroller
The invention belongs to the technical field of electronic information, and particularly relates to a contact type acoustic wave sensing device. The contact type acoustic wave sensing device includesa piezoelectric piece and a single chip microcomputer; the piezoelectric piece is used for converting a vibration signal of a sound wave into an electric signal; the single chip microcomputer is usedfor processing the received electric signal according to a pre-programmed program and issuing an execution signal. The technical problem that the sensing device has poor precision and is easy to be falsely triggered in the prior art is solved. The piezoelectric piece can convert the solid vibration signal into an electrical signal, and because the piezoelectric piece is insensitive to the acousticsignal in the air, the solid vibration signal can be better sensed, so that only one piezoelectric piece can achieve a large sensing receiving area.
Owner:广州通导信息技术服务有限公司 +1
Broken bar detection device, broken bar automation monitoring system and roller kiln
PendingCN108534547AStrict atmosphereSave I/O resourcesCharge treatment typeFurnace typesEngineeringContact type
The invention provides a broken bar detection device. The device comprises a transmission roller bar, one end of the transmission roller bar is fixedly connected with a rotating shaft which extends outwards, the tail end of the rotating shaft is fixedly connected with a trigger block suitable for rotation along with the rotating shaft, the outer side of the trigger block is fixedly provided with asignal generator corresponding to the trigger block, when the transmission roller bar rotates, the rotating shaft is driven to rotate, the trigger block is driven to rotate, and when the trigger block rotates to make contact with the signal generator, the signal generator generates a detection signal. Through the contact type broken bar detection device, multiple defects existing in the prior artcan be effectively overcome; in addition, the invention further provides a broken bar automatic monitoring system based on the contact type broken bar detection device and a roller kiln with the broken bar automatic monitoring system based on the contact type broken bar detection device.
Owner:GUANGDONG JUMPER THERMAL TECH
LED display driving circuit
ActiveCN105578663ASave I/O resourcesLow costElectrical apparatusElectroluminescent light sourcesHigh resistanceLED display
The invention relates to an electronic circuit field and particularly relates to an LED display driving circuit. The LED display driving circuit comprises a power source end, a tri-state driver, a driving module and a ground end which are connected in series, wherein the tri-state driver has three states, including high level output, low level output and high resistance output. Through changing a circuit requiring four LED ports for driving four LED lamps, only two LED ports are needed, so 50% I / O resources are saved, the cost is greatly reduced, moreover, through the LED display driving circuit, when the quantity of the LED ports is not changed, more functions can be realized.
Owner:SHENZHEN FM ELECTRONICS GRP CO LTD
A high-precision real-time clock chip
InactiveCN103226376BHigh precisionSolve electromagnetic interferenceGenerating/distributing signalsCapacitanceDigital converter
The invention discloses a high-precision real-time clock chip which comprises a clock timing module, an I2C interface module, an alarming and periodic interrupt module, a power management module and a digital temperature compensation crystal oscillator; the clock timing module comprises a second register, a minute register, an hour register, a week register, a day register, a moon register, a year register and a square wave output control register; the hour register, the day register, the moon register and the year register are connected with a combinational logic circuit; and the digital temperature compensation crystal oscillator comprises a temperature sensor, an analogue digital converter, a storage cell, a capacitor array and a crystal oscillator. The high-precision real-time clock chip provided by the invention can be repaired and adjusted within an industrial temperature range, can achieve self calibration, greatly improves the accuracy of RTC, meanwhile the problem of electromagnetic interference on macroscopic circuit wiring can be solved, and more I / O resources of the main system are saved.
Owner:SHENGZHOU HUAFENG ELECTRONICS
Method, system, device and medium for processing data
PendingCN114493856ASave memory resourcesProcessing speedInput/output to record carriersResource allocationAlgorithmTheoretical computer science
A method of processing data is disclosed. The method includes obtaining newly added data of a latest cycle, generating an incremental graph, dividing the incremental graph into a plurality of computing nodes to generate a partial incremental graph of a latest version, loading a partial incremental graph of a previous version from persistent storage, and performing processing on the partial incremental graphs of the latest version and the previous version. The invention also discloses a method for processing fund flow data, a corresponding system, a device and a medium.
Owner:ALIPAY (HANGZHOU) INFORMATION TECH CO LTD
Task application device and method based on task pre-allocation
PendingCN110532082AMeet the needs of high-priority task timelinessImprove fluencyProgram initiation/switchingRelational databasesOperating systemPriority queue
The invention relates to a task application device based on task pre-allocation, which comprises a memory and a processor, and is characterized in that an instruction is stored in the memory and is suitable for being loaded by the processor and executing the following steps: generating a task by a client; judging whether the generated task is a high-priority task; if the current task is a high-priority task, putting the current task into a high-priority queue; if the current task is not the high-priority task, selecting an entry user of the executable task, and putting the task into a pre-allocated task queue of the entry user of the executable task; entering a task application request initiated by a user; if the high-priority queue is not empty and the task with the application permissionof the input user exists, immediately applying for the task with the highest priority in the tasks by the current input user; otherwise, allocating the task with the highest priority to the current input user from the pre-allocated task queue of the current input user; and after the input user acquires the task, returning the detail data to the input user by the client.
Owner:厦门商集网络科技有限责任公司
Method and server for secondary confirmation short messaging
ActiveCN104703149AReduce processing timeSave I/O resourcesMessaging/mailboxes/announcementsSecurity arrangementComputer hardwareInformation storage
The invention discloses a method and a server for secondary confirmation short messaging. The method for secondary confirmation short messaging comprises the following steps: receiving a short message request message sent by a client, wherein the short message request message includes uplink object information; determining a client instruction corresponding to the short message request message based on the uplink object information in the short message request message; querying a table entry matched with the client instruction in a service instruction table, and determining whether the short message request message needs secondary confirmation based on the queried table entry matched with the client instruction; storing the uplink object information in a memory and sending a secondary confirmation short message to the client when determining that the short message request message needs secondary confirmation; querying uplink object information corresponding to a first confirmation short message in the memory when receiving the first confirmation short message sent by the client; and executing queried service associated with the uplink object information. By adopting the technical scheme of the invention, the efficiency processing of secondary confirmation short messages can be improved.
Owner:HANDAN BRANCH OF CHINA MOBILE GRP HEBEI COMPANYLIMITED
Method and device for automatically matching and upgrading CPLD of service board card
ActiveCN112052031AImprove output efficiencySave I/O resourcesVersion controlSoftware deploymentComputer hardwareEngineering
Owner:FENGHUO COMM SCI & TECH CO LTD
N-MOS and P-MOS permanent magnet synchronous motor driving circuit with hardware protection
The invention discloses a N-MOS and P-MOS permanent magnet synchronous motor driving circuit with hardware protection. According to the technical scheme, the novel permanent magnet synchronous motor driving circuit controls a three-phase permanent magnet synchronous motor to work and uses discrete components to drive an N-MOSFET and a P-MOSFET and comprises an MCU operation control module (1), a high-speed optical coupler isolation module (2), a reverse output module (3), an N-MOSFET control module (4), an N-MOSFET dead zone generation module (5), a P-MOSFET control module (6) and a P-MOSFET dead zone generation module (7). The middle-low grade MCU outputs a path of PWM wave, the PWM wave can be converted into two paths of complementary and symmetrical PWM waves with dead zones after passing through the driving circuit, and the power element is driven to control permanent magnet synchronous operation. According to the driving mode, the power driving chip is not used, the circuit cost is reduced, IO resources of the middle-low grade MCU are saved, the operation burden of the MCU is relieved and the generated dead zone time prevents upper and lower bridge arms from simultaneously conducting to cause circuit breakdown.
Owner:BEIJING UNIV OF TECH
Slot number identification method and device
InactiveCN109495164ASimple connection structureSave I/O resourcesTransmission monitoring/testing/fault-measurement systemsVoltageEngineering
Embodiments of the invention disclose a slot number identification method and device. The method comprises the steps of acquiring a first voltage value and a second voltage value of a first pin and asecond pin of a slot; determining a first preset voltage interval to which the first voltage value belongs and a second preset voltage interval to which the second voltage value belongs; determining afirst parameter corresponding to the first preset voltage interval and a second parameter corresponding to the second preset voltage interval; and finally calculating a slot number of the slot by using the first parameter and the second parameter. According to the slot number identification method and device, the two voltage values are collected to recognize the slot number, so that the pins andother hardware resources are saved; and more slots can be formed in a backboard with the same area, and level leads do not need to be configured, so that a connection structure of the slot is simple.In addition, only two service single-board IO pins connected with the slot need to be occupied, so that the IO resources are saved.
Owner:LUSTER TERABAND PHOTONICS TECHNOLOGY CO LTD
A digital multi-channel analog signal generation method
ActiveCN104022782BSave I/O resourcesReduce complexityDigital-analogue convertorsSignal-to-noise ratio (imaging)Time delays
The invention relates to a digital type multichannel analog signal generating method which is characterized in that an FPGA generates N paths of 1-bit-stream signals capable of having different time delays, and after the N paths of signals correspondingly sequentially pass through N paths of isolation type drivers, N paths of de-biasing circuits and N paths of filters, N paths of analog signals with high signal-to-noise ratios are output.
Owner:HARBIN ENG UNIV
Device and method for testing system-on-chip chip with multiple isomorphic IP cores
ActiveCN101788644BReduced amount of test dataAvoid time costDigital circuit testingComputer hardwareReference test
The invention discloses a device and a method for testing a system-on-chip chip with a plurality of isomorphic IP cores. The device comprises a controller and a condition comparator, wherein the controller is provided with a plurality of control signal interfaces connected to each corresponding isomorphic IP core and is used for inputting a test control signal to each isomorphic IP core, controlling the test on one or more isomorphic IP cores, broadcasting the same test excitation data to the IP cores and simultaneously controlling the output of a test response of a certain IP core; the test response serves as a reference test response and is compared with the test responses of other IP cores; and the condition comparator is used for comparing the test response of a corresponding IP core with the reference test response and processing the comparison result to produce a one-bit error identification signal for identifying whether the comparison is accordant.
Owner:LOONGSON TECH CORP
A multipath data acquisition system based on USB communication
PendingCN109902060ARealize acquisitionSave I/O resourcesArchitecture with single central processing unitMicrocontrollerData acquisition
The invention provides a multipath data acquisition system based on USB communication. The system comprises a data acquisition module, The data acquisition module comprises an A / D converter, a voltagefollower and a microcontroller, an analog input signal is filtered by the voltage follower; the signals are output to the A / D converter; the microcontroller outputs the digital signal converted by the A / D converter to a computer through the USB control chip and displays the digital signal; According to the invention, an external data acquisition system with low cost, high reliability and multiplepoints can be realized easily, so that the data transmission speed of the system can be improved, the flexibility of the system can be enhanced, and the maintenance of the system is facilitated; Andthe system can be in data communication with a PC (Personal Computer) through a USB (Universal Serial Bus) data bus interface, can display and store sampling data on the PC in real time, and can be applied to real-time acquisition of multi-path data in various occasions such as laboratories or industrial fields.
Owner:岱特智能科技(上海)有限公司
A dual-port peripheral configuration interface circuit
InactiveCN103226531BFew external portsSave I/O resourcesElectric digital data processingShift registerProcessor register
The invention belongs to the field of embedded systems, and discloses a dual-port peripheral configuration interface circuit. According to the interface circuit, only two IO interfaces are provided externally, one is an RCK (read clock) input port, and the other is an RDA (remote data access) data two-way port. A read-write data port, a read / write address signal port, and a read-write enable signal port are connected with a register set. The interface circuit comprises a clock counter, a read-write judging register, an address / data shifting register, a read data shifting register, an address register, a write enable signal generation register and a read enable signal generation register. The interface circuit disclosed by the invention has the advantages that the communication protocol and the circuit are simple, external ports are few, the communication speed changes with the rate change of an externally supplied RCK clock, an externally supplied system clock is not needed, and the like.
Owner:BEIJING UNIV OF TECH
Man-machine interaction display system capable of remotely updating pictures and audios
PendingCN110045993AImprove stabilityImprove reliabilityProgram loading/initiatingInput/output processes for data processingCapacitanceImaging processing
The invention relates to a man-machine interaction display system capable of remotely updating pictures and audios. The system comprises a core CPU, a network processing module responsible for processing data transmitted by a WLAN and WIFI, a WIFI module, a WLAN module, an image processing module, an audio processing module, a man-machine interaction module, a resistance / capacitance touch identification module and a color liquid crystal screen drive. Firstly, each module of the system is initialized; secondly, the network module receives the data and downloads encrypted image and audio data; furthermore, the core CPU packages and decomposes the data transmitted by the network processing module to the image processing module and the audio processing module, and the image processing moduleand the audio processing module performs adaptive processing ; and finally, the core CPU packages the adapted information and transmits the information to the man-machine interaction module, and the man-machine interaction module updates the data to be updated into the man-machine interaction display system to realize remote online updating.
Owner:BEIJING DWIN TECH
Backboard and mainboard connection port identification system and method, and server
ActiveCN114756484ASave I/O resourcesReduced pin countEnergy efficient computingElectric digital data processingPwm signalsParallel port
The invention discloses a backboard and mainboard connection port identification system and method and a server. The system comprises a first controller of a mainboard, a serial-to-parallel conversion chip and a plurality of downlink ports, the first controller sends PWM signals used for distinguishing the downlink ports to the serial-to-parallel conversion chip through a serial bus, and each parallel IO port of the serial-to-parallel conversion chip is connected with the corresponding downlink port through a single signal line. The serial-to-parallel conversion chip distributes the PWM signal to a downlink port connected with each parallel IO port according to the frequency; the device comprises a back plate, uplink ports of the back plate and a second controller, one end of each uplink port is connected with a certain downlink port through a cable, the other end of each uplink port is connected with an IO port of the corresponding second controller through a single signal line, and the second controller is configured to be used for analyzing PWM signals received by the uplink ports so as to determine the corresponding relation between each uplink port and the corresponding downlink port. According to the scheme, expansion of more requirements is achieved, and IO resources of the backboard are saved.
Owner:SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
A configurable low-speed pad, BMC chip with intelligent reconfigurable interface
ActiveCN107390575BWith pull-up resistor functionRealize multiplexingProgramme controlComputer controlElectrical resistance and conductanceLow speed
The invention relates to a configurable low-speed PAD and a BMC chip possessing an intelligent reconfigurable interface. The chip is characterized in that the chip includes an ARM; the ARM is connected to the configurable low-speed PADs, low-speed PADs and high-speed PADs; the ARM is connected to an interface control logic module; the interface control logic module is connected to the configurable low-speed PADs, the low-speed PADs and the high-speed PADs; the configurable low-speed PADs, the low-speed PADs and the high-speed PADs are connected to an BMC chip pin respectively; and there are the several configurable low-speed PADs, the several low-speed PADs and the several high-speed PADs. In the invention, the configurable low-speed PADs are designed, open drain output and normal output functions are possessed, and a pull-up resistor function under an I2C mode is possessed too. After the BMC chip is molded, the interface can be intelligently configured and great convenience is brought for a board-grade design. IO resources can be saved, and interface reuse of the BMC chip to 12C, SPI and PCIE is realized.
Owner:ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
Node detection method and shared storage device
ActiveCN109144415AAvoid misjudgmentSave I/O resourcesInput/output to record carriersDigital data information retrievalShared memory
The embodiment of the present application provides a node detection method and a shared storage device which are communicatively connected with a target node and can be read and written by the targetnode. The shared memory device detects the connectivity between the device and the target node according to a preset detection period; if the detection result is disconnected, the shared memory deviceis determined that the target node cannot read or write the shared memory device; if the detection result is connected, a simulated read / write operation is performed on a preset address in the sharedmemory device, and it is judged whether the target node can read / write the shared memory device according to the result of executing the simulated read / write operation. As such, frequent read and write operation of the target node can be avoided, thereby saving I / O resources of the target node.
Owner:NEW H3C CLOUD TECH CO LTD
Multimedia storage method, system and device
ActiveCN101662628BSave I/O resourcesReduce wasteSelective content distributionComputer hardwareMedia server
Owner:XFUSION DIGITAL TECH CO LTD
A method and server for secondary confirmation of short messages
ActiveCN104703149BReduce processing timeSave I/O resourcesMessaging/mailboxes/announcementsSecurity arrangementComputer hardwareInformation storage
The invention discloses a method and a server for secondary confirmation short messaging. The method for secondary confirmation short messaging comprises the following steps: receiving a short message request message sent by a client, wherein the short message request message includes uplink object information; determining a client instruction corresponding to the short message request message based on the uplink object information in the short message request message; querying a table entry matched with the client instruction in a service instruction table, and determining whether the short message request message needs secondary confirmation based on the queried table entry matched with the client instruction; storing the uplink object information in a memory and sending a secondary confirmation short message to the client when determining that the short message request message needs secondary confirmation; querying uplink object information corresponding to a first confirmation short message in the memory when receiving the first confirmation short message sent by the client; and executing queried service associated with the uplink object information. By adopting the technical scheme of the invention, the efficiency processing of secondary confirmation short messages can be improved.
Owner:HANDAN BRANCH OF CHINA MOBILE GRP HEBEI COMPANYLIMITED
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