A digital multi-channel analog signal generation method

Abstract

The invention relates to a digital type multichannel analog signal generating method which is characterized in that an FPGA generates N paths of 1-bit-stream signals capable of having different time delays, and after the N paths of signals correspondingly sequentially pass through N paths of isolation type drivers, N paths of de-biasing circuits and N paths of filters, N paths of analog signals with high signal-to-noise ratios are output.

Description

technical field [0001] The invention relates to a digital multi-channel analog signal generation method. Background technique [0002] With the rapid development of digital electronic devices and digital signal processing technology, digital devices such as FPGA, DSP, single-chip microcomputer, and ARM are gradually applied to various fields of production and life. In many fields such as sonar and radar, the multi-channel analog signal generator is a key device or system module. In particular, the phase-controlled transmission technology proposes high technical specification requirements. [0003] But the current design of digital multi-channel analog signal generator has the following problems: (1) The circuit structure is not optimized enough. Digital analog signal generators mostly adopt the design scheme of "digital device + DAC + filter", but for multi-channel analog signal generators, as the number of channels increases, the number of DACs (nbits) used will increase ...

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Problems solved by technology

[0003] However, the current digital multi-channel analog signal generator design has the following problems: (1) The circuit structure is not optimized enough

Digital analog signal generators mostly adopt the design scheme of "digital device + DAC + filter", but for multi-channel analog signal generators, as the number of channels increases, the number of DACs (nbits) used will increase accordingly, and at the same time The I / O resources occupied by digital devices are also doubled (n×number of channels), and higher requirements are put forward for high-performance digital devices with multiple I / Os. The increase in the number of I / Os occupied by DACs and digital devices consumes both A large number of hardware resources also increase the development cost; (2) High requirements for filter performance indicators

In order to ensure a high signal-to-noise ratio analog signal output, it is necessary to perform high-performance filtering on the quantization noise of the DAC output signal, which usually requires a steeper filter transition band (high enough order), and a higher order filter means Increase in circuit complexity and decrease in integration

(3) Further improvement of signal-to-noise ratio in the signal band is limited

However, since the design scheme of "DAC+filter" is still adopted to convert the digital signal into an analog signal, the circuit structure existing in the traditional digital analog signal generator is not optimized enough, and the performance index of the filter is still not solved when the multi-channel analog signal is generated. High requirements, hardware scale and development costs increase with the number of channels

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