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Configurable low-speed PAD and BMC chip possessing intelligent reconfigurable interface

A BMC chip, low-speed technology, applied in the field of IP core design, which can solve the problems of unusable special interfaces, unrealizable peripherals, and unusable new peripherals.

Active Publication Date: 2017-11-24
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, if the general-purpose IO is occupied, the addition of peripherals cannot be realized, resulting in the failure of the circuit design
[0005] The use of the above method is subject to the use of IO resources. If the IO resources are insufficient, the new peripherals cannot be used, which will affect the functions of the BMC software.
Even if IO resources are sufficient, for high-speed differential circuits, the complexity of board-level design needs to be greatly increased
In particular, some special interfaces cannot be realized by general-purpose IO simulation, which makes the circuit design regrettable

Method used

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  • Configurable low-speed PAD and BMC chip possessing intelligent reconfigurable interface
  • Configurable low-speed PAD and BMC chip possessing intelligent reconfigurable interface

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0124] Embodiment 1, BMC chip with intelligent reconfigurable interface, choose to use I2C interface:

[0125] ARM configuration control information, choose to use the I2C interface, the interface control logic module outputs control signals to the configurable low-speed PAD according to the ARM configuration control information, disables the high-speed PAD, configures the PAD to use the I2C function, and outputs signals: OUT_EN = 0, I2C_EN = 1 , I2C_SEL = 1, DIN_EN = 1.

[0126] When the low-speed PAD output data can be configured, select I2C_SIG to M7 and M1 CMOS tubes. When I2C_SIG is 0, M7 is off, M1 is on, and outputs a low level to the PAD pin; when I2C_SIG is 1, M7 is off, and M1 is off. If any bit of FREQ_SEL[2:0] is valid, it is not required outside the chip Pull-up resistor, just use a pull-up resistor, and the output high point is flat to the PAD pin.

[0127] When the low-speed PAD input data can be configured, DIN_EN = 1, select the PAD signal to M2 and M3 CMOS ...

Embodiment 2

[0128] Embodiment 2, the BMC chip of the intelligent reconfigurable interface, selects to use the SPI interface:

[0129] ARM configuration control information, choose to use the SPI interface, the interface control logic module outputs control signals to the configurable low-speed PAD according to the ARM configuration control information, disables the high-speed PAD, configures the PAD to use the SPI function, and outputs signals: OUT_EN = 0, I2C_EN = 0 , I2C_SEL = 0, DIN_EN = 1.

[0130] When the low-speed PAD output data can be configured, select SPI_SIG to M7 and M1 CMOS transistors. When I2C_SIG is 0, M7 is off, M1 is on, and outputs a low level to the PAD pin; when I2C_SIG is 1, M7 is on, M1 is off, and outputs a high level to the PAD.

[0131] When the low-speed PAD input data can be configured, DIN_EN = 1, select the PAD signal to M2 and M3 CMOS transistors, and then select the data to SPI_DIN according to I2C_SEL = 0.

Embodiment 3

[0132] Embodiment 3, the BMC chip of the intelligent reconfigurable interface, chooses to use the PCIE interface:

[0133] ARM configuration control information, choose to use the PCIE interface, the interface control logic module outputs control signals to the configurable low-speed PAD according to the ARM configuration control information, output signal: OUT_EN = 0, DIN_EN = 0, FREQ_SEL[2:0] = 0, disabled When using the transmission function, the use of pull-up resistors is prohibited; at the same time, high-speed PAD is enabled, and high-speed differential signals pass through the high-speed PAD to the PCIE module.

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PUM

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Abstract

The invention relates to a configurable low-speed PAD and a BMC chip possessing an intelligent reconfigurable interface. The chip is characterized in that the chip includes an ARM; the ARM is connected to the configurable low-speed PADs, low-speed PADs and high-speed PADs; the ARM is connected to an interface control logic module; the interface control logic module is connected to the configurable low-speed PADs, the low-speed PADs and the high-speed PADs; the configurable low-speed PADs, the low-speed PADs and the high-speed PADs are connected to an BMC chip pin respectively; and there are the several configurable low-speed PADs, the several low-speed PADs and the several high-speed PADs. In the invention, the configurable low-speed PADs are designed, open drain output and normal output functions are possessed, and a pull-up resistor function under an I2C mode is possessed too. After the BMC chip is molded, the interface can be intelligently configured and great convenience is brought for a board-grade design. IO resources can be saved, and interface reuse of the BMC chip to 12C, SPI and PCIE is realized.

Description

technical field [0001] The invention belongs to the technical field of IP core design and specifically designs a configurable low-speed PAD and a BMC chip with an intelligent reconfigurable interface. Background technique [0002] The BMC chip is a baseboard management controller chip, which has been widely used in the field of multi-channel servers. Using the BMC+IKVM remote management module, the administrator can remotely connect to the server through the remote management card, and then realize the monitoring of the server and view the remote monitored The physical characteristics of the server, such as voltage, fan speed, temperature, etc., can keep abreast of the working status of the server. [0003] In the existing BMC chip, once the design is completed, the chip structure is fixed and the peripheral interface cannot be changed. When an engineer designs a circuit, it is necessary to add a certain interface peripheral, and the peripherals are not allowed to be connec...

Claims

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Application Information

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IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/25257
Inventor 刘同强王朝辉童元满赵元
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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