238 results about "Pull-up resistor" patented technology

The invention provides an acquisition circuit, a temperature acquisition method, a circuit system and electronic equipment. The acquisition circuit comprises a first signal acquisition port, a plurality of second signal acquisition ports, a first acquisition unit and a plurality of second acquisition units. Wherein the first acquisition unit comprises a value taking resistor and a first pull-up resistor, the first pull-up resistor is located in the chip, a first reference voltage is connected to a first end of the first pull-up resistor, and a second end of the first pull-up resistor is connected with a first end of the value taking resistor through a first signal acquisition port; the second acquisition unit comprises a second pull-up resistor and a thermistor, the second pull-up resistor is located in the chip, the first end of the second pull-up resistor is connected with the first reference voltage, and the second end of the second pull-up resistor is connected with the first end of the thermistor through a second signal acquisition port. Therefore, the acquisition circuit can realize voltage acquisition of one end of the thermistor by using a simple circuit, so that the acquisition circuit is low in cost and simple in wiring design.

The utility model relates to the field of PC (Personal Computer) electrified clearing CMOS (Complementary Metal Oxide Semiconductor), in particular to a circuit structure based on a PC electrified clearing CMOS, which comprises an SIO circuit, an electrified clearing CMOS circuit and a PCHRTCRSTR, a signal input pin of the PCHRTCRSTR is connected to a grid electrode of Q31, a source electrode of the Q31 is connected with + 3V3RTC, a drain electrode of the Q31 is connected to a grid electrode of QS3, the grid electrode of the QS3 is indirectly controlled by a drain electrode of the Q31, a source electrode of the QS3 is connected to VBATSIO, and the source electrode and the drain electrode of the QS3 are connected to the ground through a pull-up resistor. And the grid electrode of the Q20 is directly controlled, the grid electrode of the Q20 is influenced by the level of the drain electrode of the QS3, the source electrode of the Q20 is connected to the + 3V3RTC, and the drain electrode of the Q20 is output to the VBATSIO.

The invention provides control equipment and a control method, which can be applied to the technical field of bus drive control. The control device comprises a signal detection module, the input end of the signal detection module is connected with a target bus, the signal detection module is used for detecting a time sequence signal of the target bus, and the target bus is used for electrically connecting a master device with a plurality of slave devices; the control module is used for generating a resistance adjusting signal according to the difference between the detection value of the time sequence signal and a preset range; the controllable pull-up resistor is electrically connected with the target bus and used for adjusting the resistance value of the controllable pull-up resistor according to the resistance adjusting signal, and the controllable pull-up resistor is used for pulling up the voltage of a signal line in the target bus to a preset level.

The invention discloses a zero-voltage turn-on circuit and a zero-voltage turn-on method of a switching tube in a switching power supply, and belongs to the technical field of circuits. In a critical conduction mode, when a low-side power tube is turned off, the rising edge zero-voltage starting circuit compares a switch node voltage with an input voltage or compares the switch node voltage with an output voltage under the control of a low-side gate driving voltage, outputs a high level to a high-side gate driving end when the switch node voltage is equal to the input voltage or the output voltage, and outputs a low level to a low-side gate driving end when the high level is equal to the output voltage. A high-side power tube is controlled through a high level to realize zero-voltage starting; in a critical conduction mode, when the high-side power tube is turned off, the falling-edge zero-voltage starting circuit compares an induced voltage with a pull-up resistor voltage under the control of a high-side gate driving voltage, outputs a high level to a low-side gate driving end when the induced voltage is equal to the pull-up resistor voltage, and controls the low-side power tube to realize zero-voltage starting through the high level. The induced voltage is equal to the sum of the pull-up resistor voltage and the switch node voltage. According to the invention, the transmission delay can be reduced.

The invention provides a liquid leakage detection circuit, a mainboard and a liquid cooling server, and relates to the technical field of liquid cooling server design. The circuit comprises a differential signal generation module, a signal comparison module and a logic judgment module, the differential signal generation module comprises two liquid leakage detection cables, one liquid leakage detection cable is connected to a power supply voltage through a pull-up resistor, the other liquid leakage detection cable is grounded through a pull-down resistor, the two detection cables form a differential wiring pair in a PCB layout, and the signal comparison module is connected with the logic judgment module. The signal generator is used for generating differential detection signal pairs; the input end of the signal comparison module is connected with the detection cables, and the signal comparison module is used for outputting a differential voltage signal corresponding to the impedance change between the two detection cables based on the signal pair; and the logic judgment module is connected with the output end of the signal comparison module and is used for judging whether liquid leakage occurs or not based on the differential voltage signal and a preset threshold voltage signal. By adopting the differential signal design, noise interference can be reduced, and the problem of liquid leakage false alarm caused by noise interference is remarkably improved.

An integrated circuit is provided for driving the gate of a GaN power switch transistor in a switching power converter. During a first portion of an on-time period for the GaN power switch transistor, the integrated circuit charges the gate through a relatively high pull-up resistance. During a second portion of the on-time period, the integrated circuit charges the gate through a relatively low pull-up resistance. During a first portion of an off-time period for the GaN power switch transistor, the integrated circuit discharges the gate through a relatively low pull-down resistance and then discharges the gate through a relatively high pull-down resistance in response a voltage of the gate falling below a threshold voltage.

The embodiment of the invention provides a single-bus communication method and device, a chip and a medium, and the method comprises the steps: enabling a host to enter an initialization mode after the host confirms that an internal power supply and a clock of a slave are stable; the host sends a wake-up code to the slave within a set time to wake up the slave, and releases the bus to enter a normal communication mode; the host sends a communication signal to the slave through the improved communication frame; after the host receives a response signal of the slave, the host releases the bus, the bus is pulled to a high level from an external pull-up resistor, and the transmission is ended; wherein the format of the improved communication frame comprises ten codes, one code corresponds to one bit, and the ten codes sequentially comprise one start bit, six address bits, one read-write control bit, one data bit and one response bit. A wake-up code is set before communication between the host and the slave, so that the slave is prevented from being mistakenly waken up. According to the communication mode, the coding mode is simplified, the chip area is reduced, and the transmission speed of the chip is also improved.

The present invention belongs to the field of intelligent monitoring technology, specifically relating to a health monitoring system and its preparation method. The system comprises a health monitoring mask and a host computer. The health monitoring mask includes the mask and its built-in respiratory monitoring unit, heart rate monitoring unit, and health monitoring unit. The host computer includes a display interface and its built-in data processing module. The respiratory monitoring unit includes a thermoelectric device made of P-type and N-type semiconductor thermoelectric particles. The heart rate monitoring unit consists of a MAX30102 integrated on a flexible PCB, a voltage regulator circuit, a decoupling capacitor, and a pull-up resistor. The health monitoring unit is sewn into the mask and includes an ADC conversion unit I, a microcontroller chip with a built-in Bluetooth module and an integrated circuit bus. The host computer includes a display interface and a data processing module to receive monitoring data from the respiratory monitoring unit and the heart rate monitoring unit, match the data into groups, and perform multi-source fusion. Based on the multi-source fusion data, the health status of the human body can be identified and judged.

This signal transmission device comprises: a transmission line (2) having a signal line (21) and a reference line (22); and a termination circuit (3). One end of the signal line (21) of the transmission line (2) is electrically connected to a signal output terminal (101) of a transmitter (100) that transmits an electrical signal, and the other end of the signal line (21) of the transmission line (2) is electrically connected to a signal input terminal (201) which is electrically connected to a constant power supply potential node (203) via a pull-up resistor (204) in a receiver (200) that receives the electrical signal from the transmitter (100). The reference line (22) has a first conductor (221) considered to be ground potential, a second conductor (222) that is DC-isolated from the first conductor (221), and a capacitor (22a) that connects the first conductor (221) and the second conductor (222). The termination circuit (3) is electrically connected to the other end of the signal line (21) of the transmission line (2) and applies a constant voltage, which is a voltage below the constant power supply voltage applied to the constant power supply potential node (203) of the receiver (200), to the other end of the signal line (21) of the transmission line (2).

The invention discloses a universal input / output interface, and belongs to the technical field of transmission interfaces of digital circuits and analog circuits, the universal input / output interface comprises a TX module, an RX module and a withstand voltage protection circuit, and the TX module comprises a first phase inverter; a second inverter; a first AND gate; a second AND gate; a first NAND gate; a second NAND gate; a third NAND gate; a third AND gate; a bias circuit; a level conversion circuit; a buffer; a first pmos tube; a second pmos tube; a first nmos tube; a second nmos tube; a third pmos tube; a fourth pmos tube; the RX module comprises a Schmitt trigger; a first switch; a pull-up resistor; a pull-down resistor; a second switch; the withstand voltage protection circuit comprises a third nmos tube to a seventh nmos tube; a fifth pmos tube to a tenth pmos tube; the electrostatic discharge protection circuit includes a p-type diode and an n-type diode. The range of the output level signal is selectable, and the application scenarios of the circuit can be increased.

A delay-adjusted digital-unit interface comprises a first node, a second node, a third node, and an amplifier assembly. The first node is connected to a pull-up resistor and can be connected to the signal line of a transmission line connected to a first digital unit at a distal point. The second node is configured to be connected to a second reference electrical potential, a signal-return line of the transmission line, and a signal-return line of a second digital unit. The third node can be connected to a signal line of the second digital unit. The amplifier assembly is configured to be connected between the first node and the third node, to transform between high electrical potentials on the first node and lower electrical potentials on the third node, and to diversely delay low-to-high and high-to-low signal transitions transmitted by the second digital unit during communication with the first digital unit.

The embodiment of the present application provides a detection circuit and method, the detection circuit comprises: a first MOS transistor, a voltage division unit and a pull-up resistor; the first end of the voltage division unit is connected with the positive pole of a 2PIN battery, the second end of the voltage division unit is connected with the gate of the first MOS transistor, the third end of the voltage division unit is connected with the source of the first MOS transistor, and the third end of the voltage division unit is grounded; the drain of the first MOS transistor is connected with a power supply through the pull-up resistor; the first MOS transistor is used for outputting an indication signal; wherein the indication signal is a signal used for indicating whether the 2PIN battery is connected with a target device; when the 2PIN battery is connected with the target device, the 2PIN battery is used for supplying power for the target device. The detection circuit provided by the embodiment can overcome the problems of the existing detection technology, such as complicated steps, high cost and high current consumption.

A device for transmitting first data to an external device and receiving second data from the external device is provided. The device includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; a current source circuit connected to a second node and including a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit, based on the first data; a receiver connected to the second node and configured to obtain the second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

Embodiments of the present disclosure disclose an electronic device supporting Type-C connection, comprising: a dual role port (DRP); and a controller coupled to the DRP and performing: detecting whether the DRP is connected to a peer device; in response to detecting that the DRP is connected to the peer device, detecting whether the DRP is connected to a pull-up resistor on the peer device; in response to detecting that the DRP is connected to the pull-up resistor on the peer device, confirming whether the electronic device has power supply capability; and after confirming that the electronic device has the power supply capability, inquiring whether the peer device supports becoming a sink role.

This invention discloses an interface power supply circuit and a terminal. The circuit includes: a VBUS power network for a USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2. The control terminal of the PMOS transistor VT2 is connected to the drain of both the NMOS transistor Q3 and the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the terminal's system power supply VDD_5V to supply power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network via a pull-up resistor R1. The control terminal of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2. The source of the NMOS transistor Q1 is connected to the GND ground terminal. This provides a more stable interface power supply solution, improving the operational stability of the terminal and enhancing the user experience.

The invention provides an OCP network card resource allocation method and electronic equipment. The method comprises the steps that a first CPLD recognizes the connection state between an OCP network card and a CPU and sends the recognized connection state between the OCP network card and the CPU to a BMC, and the BMC further controls the OCP network card to allocate corresponding bandwidth resources for each CPU based on the connection state between the OCP network card and the CPU. Thus, the BMC can automatically control the OCP network card to allocate corresponding bandwidth resources to each CPU through the connection state between the OCP network card and the CPU identified by the CPLD, welding of electrical elements such as a pull-up resistor and a pull-down resistor on a mainboard is not needed, and then the level value of the BIF pin is not needed to be configured by manually adjusting the pull-up resistor or the pull-down resistor. Therefore, automatic and accurate allocation of OCP network card bandwidth resources can be realized, and the automatic and intelligent management level of the electronic equipment is improved. The production complexity and the risk of human errors caused by manual hardware configuration can be avoided, and the manufacturing, operation and maintenance cost is reduced.

The purpose of the present invention is to suppress the occurrence of malfunctions and malfunctions in an encoder via a communication line when the encoder is detached from and attached to a control device. A control device (2) controls a motor (4) on the basis of a detection signal from an encoder (3) that detects the operating position of the motor (4). A control device (2) is provided with a communication unit (22), a pull-up resistor (R1), a first power source (26), a first switch (SW1), and a control unit (27). The communication unit (22) transmits and receives the detection signal to and from the encoder (3) via the communication line (L2). The pull-up resistor (R1) is connected to the communication line (L2). A first switch (SW1) is provided in a first circuit (L7) that connects a first power source (26) and a pull-up resistor (R1), and turns on and off the first circuit (L7). The control unit (27) controls the first switch (SW1).

According to the three-phase brushless motor split-phase driving method, six single-phase brushless motor delay starting operation modules are symmetrically arranged on the two sides of each phase of stator magnetic poles, the distance between the modules is equal to the pole distance of rotor magnetic poles, and the modules are distributed at equal angles according to a specific sequence. The module comprises a parallel Hall and a pull-up resistor, an output signal of the module directly controls an H-bridge power switch, and adjustable dead time and a conduction angle of 50 ns to 10 microseconds are provided through turn-off and turn-on delay control, so that a line segment control commutation mechanism is formed. The system is composed of a three-phase stator winding, a delay starting module and an H-bridge driving circuit. Complex algorithms and hardware are omitted, the cost is reduced, the structure is simplified, commutation can be accurately controlled, the operation stability and efficiency are improved, and the three-phase brushless motor also has redundancy and self-power-generation functions. The method has wide application prospects in the fields of industry, traffic and the like. According to the embodiment verification, the performance is obviously superior to that of a traditional scheme.

A kind of control loop pulse width adjustable timer locking circuit and method, the circuit includes working power supply, first, second 555 timer chip U1, U2, three input or gate chip U3 and button switch S1;The power supply pin of working power supply VCC is connected to two 555 timers and three input or gate chip, the 2 number trigger pin of U1, U2 is connected;The 3 number output pin of U1, U2 and the pin of button switch S1 are respectively connected to the input end of U3, the output end of U3 is connected to the 2 number trigger pin of U1, U2, and is connected to VCC with a pull-up resistor R1, the other end of S1 is grounded;And the pulse width of U1 is less than U2.The control loop pulse width adjustable timer locking circuit and method of the present application can accurately modulate the test jump pulse width of control loop, and can only trigger once within a certain time, to avoid multiple triggers leading to undesirable consequences, effectively guarantee the stability of load control system.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A data line and a charging device are provided. The data line includes a Type-A interface, a first interface, a wire, and a circuit identification module. The Type-A interface is correspondingly connected to a VBUS pin, a D+ pin, a D− pin, and a GND pin in the first interface. The circuit identification module includes a pull-up resistor, a switch circuit, a filter circuit, and a comparator circuit. The comparator circuit controls the first end and the second end or the third end of the switch circuit to be connected.

Embodiments of the present application provide a method and device for determining a driving resistance, a testing machine and a storage medium. The method is applied to the testing machine and includes: obtaining a first output voltage value of a first driving circuit in the memory when the driving resistance is turned on while outputting data from an output pin of the memory; the first driving circuit includes a pull-up resistor and a pull-down resistor, and the driving resistance includes the pull-up resistor or the pull-down resistor; obtaining a test resistance value of a test circuit of the testing machine, a power voltage value of the first driving circuit, and a first voltage value applied to the test circuit when the driving resistance is turned on; the test resistance of the test circuit and the driving resistance of the first driving circuit form a series circuit when the driving resistance is turned on; and determining the resistance value of the driving resistance according to a voltage division law of the series circuit based on the first output voltage value, the test resistance value of the test circuit, the first voltage value and the power voltage value.

A system and method for operating an output driver are disclosed, the method comprising connecting a first P-channel field-effect transistor (PFET) between a supply voltage and an output node; connecting a second PFET in parallel with the first PFET between the supply voltage and the output node; connecting a first N-channel field-effect transistor (NFET) between the supply voltage and a gate of the second PFET; and adjusting a voltage at a gate of the first NFET based on a voltage at the output node to modulate a voltage of a gate of the second PFET to maintain a pull-up resistance within a predefined range.

Methods, devices, or systems can be used to detect wire breaks in battery modules, such as those found in electric vehicles. These methods, devices, or systems may involve comparing voltage measurements from even and odd-numbered battery cells with pull-up resistors enabled and disabled. By using simultaneous measurements and determining comparisons between adjacent cells, the method can compensate for load fluctuations that might lead to false detections. The approach can be executed within a fault-tolerant time interval, allowing for the timely implementation of safety measures when a fault is detected.

An integrated circuit is provided to drive the gate of a GaN power switching transistor in a switching power converter. During the first part of the on-time period for the GaN power switching transistor, the integrated circuit charges the gate through a relatively high pull-up resistor. During the second part of the on-time period, the integrated circuit charges the gate through a relatively low pull-up resistor. During the first part of the off-time period for the GaN power switching transistor, the integrated circuit discharges the gate through a relatively low pull-down resistor and then discharges the gate through a relatively high pull-down resistor in response to the gate voltage falling below a threshold voltage.

The present application provides a low-power bistable self-locking key circuit and a wireless charging system, wherein the key circuit includes a key, a switch module, a driving capacitor, a voltage-dividing resistor, and two switching modules; when the key is pressed, two separate contacts are connected; the first end of each switching module is connected to the power supply end through a pull-up resistor, and the second end of each switching module is connected to the ground end; the first end of each switching module is also connected to the enable end and a contact of another switching module; the voltage-dividing resistor is connected in series between the first end of one of the switching modules and the contact connected thereto, and the driving capacitor is connected in series between the contact and the ground end; the switch module is connected in series between the power supply path between the power supply end and the output end, and its enable end is connected to the first end of one of the switching modules. The key circuit provided by the present application has low power consumption, is sensitive to response, and does not require a separate power supply.

The application provides a solid rocket engine ignition circuit capable of preventing the control system control output end from being reset transiently and mis-triggered. The control end reset transient high level is prevented from being mis-triggered, and a simple logic module and a pull-up resistor are adopted to prevent the control system control output end from being reset transiently and mis-triggered. The pull-up resistor connected to the output end of the control module makes the control signal output by the control module in a high state during the reset period. The logic module is inverted to a low level signal, so that the high level signal output by the control module during the power-on reset period can be effectively prevented from directly causing the ignition module to be mis-triggered.

The present invention discloses a board status monitoring system and method suitable for OTN and WDM equipment. The system includes a main control board, a backplane, and n single boards. The backplane is provided with n parallel-connected resistor components. Each single board is provided with a working ground and a reference power supply. The resistor components include pull-up resistors and pull-down resistors. The main control board is provided with an A / D detection circuit, a main control board reference power supply, and a main control board pull-up resistor. The resistor components are connected in parallel to the A / D detection pin on the main control board. The A / D detection pin on the main control board is also simultaneously connected to the input end of the A / D detection circuit and one end of the main control board pull-up resistor. The other end of the main control board pull-up resistor is connected to the main control board reference power supply. The present invention is based on the board status detection system and detection method provided by routers, switches, EPON, GPON, OTN, WDM, DWDM, and DCI equipment. It can save backplane space and connector pin resources on the main control board side and can also determine the power-on status of each single board.

Various configurations of high-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral, and methods of operating the same, are provided to improve the Remote Wake sequence. Repeaters include circuitry to detect the start of Resume signaling or the end of Resume, following initiation of Remote Wake. In an example, pull-up resistors coupled to upstream differential signal lines and a detection circuit with a current source are controlled to detect the start of Resume signaling. In another example, the upstream-side pull-resistors and an enable signal to an upstream-side transmitter are controlled to detect the end of Resume.

The utility model relates to the technical field of low-power-consumption circuits, in particular to a low-power-consumption remote controller circuit for a frequency converter, which comprises a power input circuit, a pull-up resistor R1, a pull-down resistor R21, a first boost low-power-consumption power converter and a second boost low-power-consumption power converter. The first boost type low-power-consumption power converter and the second boost type low-power-consumption power converter are connected to the power input circuit. The second boost type low-power-consumption power converter is connected with the power input circuit through a pull-up resistor R1, and the first boost type low-power-consumption power converter is grounded through a pull-down resistor R21. According to the utility model, the main control unit can control the closing of the first boost type low-power-consumption power converter through the enable signal, so that the dynamic management of the power consumption of the module supplied by the first boost type low-power-consumption power converter is realized, and the power consumption is reduced.