AES decryption and decryption method and circuit for FPGA with limited IO resource

An encryption, decryption, resource technology, applied in the field of communication, can solve problems such as too many pins, cannot meet AES encryption and decryption, and increase device cost, so as to achieve the effect of improving utilization rate, strong program portability, and saving IO resources

Active Publication Date: 2016-06-29
上海航天智能装备有限公司
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0008] In the process of using FPGA to implement AES encryption and decryption under the existing technical conditions, a large number of IO pin resources need to be used. On the one hand, the cost of the device will be greatly increased. And the number of pins required for decryption is large, which cannot meet the needs of AES encryption and decryption

Method used

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  • AES decryption and decryption method and circuit for FPGA with limited IO resource
  • AES decryption and decryption method and circuit for FPGA with limited IO resource

Examples

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Effect test

Embodiment

[0059] Such as figure 2 As shown, an AES encryption and decryption method suitable for FPGAs with limited IO resources includes the following steps:

[0060] 1) The data processing module receives the input data and caches it in the input buffer area, specifically including the following steps;

[0061] 11) Determine whether the reset signal r is 1, if so, reset all registers, and return to step 11); if not, proceed to step 12);

[0062] 12) Determine whether the write address initialization signal a1 is 1, if so, reset the input cache write address pointer, and return to step 11); if not, proceed to step 13);

[0063] 13) Determine whether the input buffer enable signal E_i is on a falling edge, if so, write the received data into the input buffer, and the address pointer is incremented by 1; if not, return to step 11);

[0064] 2) The FPGA chip sends the data in the input buffer area to the encryption unit or the decryption unit through a control command, specifically inc...

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Abstract

The invention relates to an AES (Advanced Encryption Standard) decryption and decryption method for FPGA with limited IO resource. The AES decryption and decryption method includes the following steps: 1) a data processing module receives the input data and buffers the data into an input buffer cache; 2) an FPGA chip sends the data input in the buffer cache to an encryption unit or a decryption unit through a control command; 3) the FPGA chip sends the encrypted or decrypted data to an output buffer cache through the control command; 4) the FPGA chip reads the data in the output buffer cache through the control command; and 5) a system state signal is sent through a state manager and a command module. Compared with the prior art, the AES decryption and decryption method and circuit for FPGA with limited IO resource have the advantages of saving IO resource and being high in the program transportability.

Description

technical field [0001] The invention relates to the communication field, in particular to an AES encryption and decryption method and circuit suitable for FPGAs with limited IO resources. Background technique [0002] With the development of the Internet of Things, radio frequency communication has gradually become a common way of information exchange. With the development of modernization, the security of this information exchange method is increasingly threatened by various aspects. Therefore, it is necessary to carry out information encryption protection on the radio frequency communication method under the framework of the Internet of Things. Information encryption technology is the core technology to ensure information security. Transmission encryption is mainly used in the communication link system of the Internet of Things. There are many kinds of information encryption algorithms, and the most common algorithm used in data communication is the AES algorithm. The A...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06
Inventor 廖超陆峰
Owner 上海航天智能装备有限公司
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