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Scalar operation unit structure supporting floating-point division method in GPDSP

A technology of scalar operation and unit structure, which is applied in the calculation of using number system representation, calculation, calculation using non-contact manufacturing equipment, etc., can solve the problem of high complexity of division hardware algorithm, inability to obtain floating-point division, and iterative calculation time Long and other problems, to achieve the effect of satisfying portability and area controllability, simple structure and good feasibility

Inactive Publication Date: 2016-02-17
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

This implementation has a small area, but it is impossible to obtain the floating-point division results of the IEEE-754 standard through an iterative method, and compared with direct hardware implementation, the iterative calculation time of this method is longer
[0004] Due to the high complexity of the division hardware implementation algorithm, complex design structure, and large occupied area, it is generally not necessary to directly design the division component in the vector component with high parallelism.

Method used

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  • Scalar operation unit structure supporting floating-point division method in GPDSP
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  • Scalar operation unit structure supporting floating-point division method in GPDSP

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Embodiment Construction

[0034] The present invention will be further described in detail below with reference to the drawings and specific embodiments of the specification.

[0035] Such as figure 1 Shown is the position of the scalar operation unit (SPE) of the present invention in the processor. The scalar arithmetic unit SPE of the present invention is located in the scalar processing unit SC of the processor, and receives scalar arithmetic instructions distributed by the dispatching component in the instruction flow control unit, decodes and sends them to the corresponding functional arithmetic unit in the SPE for execution. The scalar processing unit SC also contains a scalar data fetching unit, which can realize scalar fetching instruction decoding, address calculation and data write back and other fetching pipeline control, and can also provide data support for SPE; at the same time, SPE can also provide scalar The memory access unit provides related operations such as address processing and data...

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Abstract

The invention discloses a scalar operation unit structure supporting a floating-point division method in a GPDSP. The scalar operation unit structure comprises a first component SMAC1, a second component SMAC2 and a third component SIEU, which are used as scalar calculation components and are used for supporting the scalar basic calculation; each scalar calculation component corresponds to one scalar instruction in a VLIW execute packet. The scalar operation unit structure has the advantages that the instruction execution periods are few; the delay is small; the structure is simple; the feasibility is high, and the like.

Description

Technical field [0001] The invention mainly relates to the field of microprocessors, and specifically refers to an implementation structure of a scalar arithmetic unit suitable for supporting floating-point division in a high-performance general-purpose DSP (GPDSP) chip. Background technique [0002] With the rapid development of digital services driven by the Internet, mobile communications, consumer electronics, and multimedia technologies, people need more powerful digital signal processors to handle huge data services. For example, high-definition 2D or 3D digital image processing, radar signal processing, autonomous navigation information processing, mobile communications, etc. Because these algorithms are data-intensive, they involve a large number of basic operations such as floating-point, fixed-point, logic, and complex numbers, and division. In particular, the performance of division, single-precision floating-point division or double-precision floating-point division ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52G06F7/50G06F9/38
CPCG06F7/52G06F7/50G06F9/3887
Inventor 彭元喜雷元武彭浩陈书明郭阳刘祥远田甜徐恩胡封林刘仲孙永节陈虎刘胜王耀华吴虎成
Owner NAT UNIV OF DEFENSE TECH
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