Goldschmidt algorithm-based floating-point divider

Abstract

The present invention discloses a Goldschmidt algorithm-based floating-point divider. The Goldschmidt algorithm-based floating-point divider comprises: an iterative initial value generator for generating an approximate value of a reciprocal of a mantissa of a divisor, wherein the approximate value is accurate to 14 bits; a Goldschmidt algorithm iteration module comprising two multipliers, one adder and one iterative control state machine, wherein the iterative control state machine is used for controlling a Goldschmidt algorithm iteration process, and filling a multiplier pipeline station by scheduling three continuous division instructions; and a normalization processing module for performing floating-point number exception determination and sign bit, exponent and mantissa specification, and normalizing a quotient result with different operation accuracy of a dual-accuracy floating-point division or single-accuracy floating-point division. The Goldschmidt algorithm-based floating-point divider disclosed by the present invention has the advantages of short instruction execution period, short delay, simple structure, high feasibility and the like.

Description

Technical field [0001] The present invention mainly relates to the field of microprocessor arithmetic components, and specifically refers to a method suitable for implementing high-speed floating-point division operations in a processor by multiplexing multipliers in the design of high-performance general-purpose DSP (GPDSP) chips, especially a Implement double-precision floating-point division or single-precision floating-point divider on the hardware platform. Background technique [0002] A large number of single-precision floating-point operations or double-precision floating-point operations are required in fields such as scientific computing applications, commercial applications, and entertainment applications. With the rapid development of VLSI technology, floating-point logic has become a basic part of high-performance computer systems. The processing speed of floating-point arithmetic components limits the performance of applications that require a large amount of float...

AI Technical Summary

Problems solved by technology

[0004] The divider based on the SRT algorithm has the advantages of simple structure and small area overhead, but its operation speed is far behind the iterative algorithm based on multiplication.

Multiplication is required in the iterative process of the divider implemented by the multiplication algorithm, so the hardware implementation circuit must include a multiplier, which often has a relatively large area cost.

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