Secure testability design structure of encryption chip

Abstract

The invention discloses a testability design structure for protecting an encryption chip from scanning attacks. The secure testability design structure of the encryption chip is introduced with key shielding logic, shift enabling logic and a secure scan controller based on the conventional scan design structure. If the encryption chip first enters the functional mode after power-on or reset, the key shielding logic allows the key to be loaded under the control of the security scan controller, while the shift enabling logic prevents the circuit from switching to the test mode, thereby avoidingthe leakage of the encrypted information. Conversely, if the encryption chip first enters the test mode after power-on or reset, the scan shift and the response capture can be performed normally underthe control of the security scan controller, while the key is isolated, thereby ensuring that the data removed from the scan chain is independent of the key. According to the secure testability design structure of encryption chip, by adding less hardware logic, all potential scan-based side channel attacks can be resisted while ensuring the circuit testability.

Description

technical field [0001] The invention belongs to the field of hardware security, and more specifically relates to a testability design structure for protecting an encryption chip from scanning attacks. Background technique [0002] In order to protect the integrity and confidentiality of data, encryption algorithms are widely used in the field of information security, among which the Advanced Encryption Standard AES encryption algorithm is one of the most popular algorithms in symmetric key encryption. In many cases, encryption algorithms are implemented in hardware because hardware implementation has many advantages over software implementation, for example, it can provide a high data throughput rate. In hardware implementations of cryptographic algorithms, the keys are usually stored within the module and cannot be easily accessed. Since the encryption chip has zero tolerance for failure, it should be rigorously tested to ensure that it will function properly. Scanning de...

AI Technical Summary

Problems solved by technology

A scan-based attack is easier to execute, so it has a greater potential threat than an attack based on side-channel parameters such as timing, power consumption, and electromagnetic emissions

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