Safe password chip testability design structure in boundary scanning design environment

Abstract

The invention discloses a testability design structure for protecting an AES password chip from scanning attack in a boundary scanning design environment. According to the safe testability design structure, shift enable logic, scan chain mode switching reset logic and key isolation logic are introduced on the basis of a conventional boundary scan design structure. The shift enable logic is used for disabling a scanning shift operation in a functional mode; the scan chain mode switching reset logic enables the chip to execute a reset operation at first when switching from a function mode to a test mode, so that confidential information stored in the scan chain is protected; and the key isolation logic is used for isolating the encryption key in the test mode so as to prevent the attacker from obtaining the key information in the test mode. New input and output signals are not introduced, only little hardware expenditure is needed, the chip can be automatically protected, and all potential side channel attacks based on scanning can be resisted on the premise that the testability of the circuit is not damaged.

Description

Technical field [0001] The invention belongs to the field of chip security, and more specifically, relates to a security testability design structure for protecting cryptographic chips from scanning-based non-intrusion attacks. Background technique [0002] With the development of emerging technologies such as the Internet of Things and big data, information security and privacy have become more and more important, and cryptographic algorithms have been widely used. Since the data throughput rate provided by software implementation is low, and more computing resources are required, cryptographic algorithms are usually implemented by hardware modules. The encryption algorithm has zero tolerance to failure, so the encryption hardware needs to be strictly tested. [0003] Scanning design improves the controllability and observability of the internal triggers of the chip, and converts the test of sequential circuits into the test of combinational circuits, which brings great convenien...

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Problems solved by technology

[0005] In the existing patents, no patented invention similar to the testability design structure of the secure cryptographic chip under the boundary scan design environment was found

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