Register resetting method and device based on scanning mode

A technology of scanning mode and reset method, applied in the field of register reset method and device based on scanning mode, can solve problems such as false reset, and achieve the effects of simplifying reset logic, reducing workload, and simplifying design

Active Publication Date: 2013-04-03
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the reset control module must accurately control the data sequence scan

Method used

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  • Register resetting method and device based on scanning mode
  • Register resetting method and device based on scanning mode
  • Register resetting method and device based on scanning mode

Examples

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Embodiment Construction

[0019] Such as figure 2 As shown, the implementation steps of the register reset method based on the scan mode in this embodiment are as follows:

[0020] 1) Build a scan chain with all registers, and connect the data input and data output terminals of the registers in the scan chain that need to be reset to 1 in series with a NOT gate;

[0021] 2) Continuously input the reset value 0 to the head of the scan chain, and the registers that need to be reset to 1 are converted to the reset value 1 by the received reset value 0 through the NOT gate connected in series at the data output terminal, and then reset to 1, and the registers that need to be reset to 0 are directly reset to 1. Reset to 0 according to the reset value 0 received; the reset value 0 is output to the next register along the scan chain, and finally completes the reset of all registers.

[0022] In this embodiment, for the registers that need to be reset to 1, a NOT gate is added before the data input terminal ...

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Abstract

The invention discloses a register resetting method and device based on a scanning mode. The register resetting method comprises the following steps of: (1) constructing scan chains for all registers, respectively connecting data input ends and data output ends of the registers in the scan chains with a not gate, wherein the registers need to be reset to 1; and (2) continuously inputting a reset value 0 to the head of the scan chain. The register resetting device comprises a resetting control logic and a clock control logic which are respectively connected with each register; the register resetting device also comprises reset value converting units, the number of which is in one to one correspondence with the number of the registers needing to be reset to 1; each reset value converting unit comprises two not gates, wherein one of the not gates is connected with the data input end of the corresponding register in series, and the other not gate is connected with the data output end of the corresponding register in series. According to the register resetting method and device, the logic design can be simplified, the realization of resetting logic is transparent for testability design, and the workload of testability design can be reduced.

Description

technical field [0001] The invention relates to the field of registers of microprocessors, in particular to a register reset method and device based on a scan mode. Background technique [0002] In microprocessor design, it is necessary to reset registers, memory and other structures in a certain way, so that the microprocessor can have a definite initial state. For register reset, there are two common methods: synchronous reset and asynchronous reset. Whether it is a synchronous reset or an asynchronous reset, it involves the wiring of the global reset signal. This is because there are a large number of registers in the design of the microprocessor, and the reset signal must be sent to each register that needs to be reset, and the load is very heavy, and the registers are spread all over the microprocessor chip, and the delay of the reset signal line is also relatively large. As the scale of the processor chip increases, the number of registers increases; in addition, the...

Claims

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Application Information

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IPC IPC(8): H03K17/22
Inventor 孙彩霞王永文张承义高军倪晓强窦强隋兵才陈微赵天磊王蕾黄立波
Owner NAT UNIV OF DEFENSE TECH
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