A method and a system for designing the testability of a high-speed serial IO interface based on DLL clock recovery

Abstract

The invention discloses a method and a system for designing the testability of a high-speed serial IO interface based on DLL clock recovery. The idea of the method is that a DLL clock recovery may provide a group of clocks with different phases, that a control and selection signal of a DLL testing control unit is set, that a sampling point testing clock can be generated by using the group of clocks with different phases, that data is sampled at different positions of a UI, that a built-in BERT generates a test vector in order to perform detection and statistic on bit errors and test a bit error rate bathtub curve, and that then a jitter separation program fits random jitter and deterministic jitter according to a gating point and bit error rate information and estimates bit error rate. The method is also capable of testing parameters such as jitter tolerance, and sensitivity or the like and provides a condition for system-level testability. An internal clock is used as a testing clock so that high testing precision is guaranteed. A built-in testing circuit has a small scale and is easy to produce. A testing process does not relate to the use of ATE. Therefore, cost of testing the high-speed serial IO with a desk-type instrument can be effectively reduced and testing time is shortened.

Description

technical field [0001] The invention relates to a testability design method for a high-speed serial IO interface, in particular to a testability design method and system for a high-speed serial IO interface based on DLL clock recovery. Background technique [0002] With the increase of processor speed, I / O becomes the bottleneck that limits system-level performance, and improving I / O performance is very critical to improving system performance. In the past 40 years, the I / O interconnection between chips mainly uses parallel bus technology. In order to improve system performance, the data rate and clock rate continue to increase, and the skew between parallel data has an increasing impact. Although the Source Synchronous (SS) technology can avoid data skew by sending strobe signals, due to the limitations of the parallel signal itself, the parallel transmission method gradually becomes incapable when the transmission rate increases. Therefore, the serial signal transmission ...

AI Technical Summary

Problems solved by technology

However, the loop test is only a pass / fail test, which is a functional test and cannot obtain parameter information; if the bit error rate requirement is low and the number of bits to be sent is huge, the test time will become very long

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