Method and apparatus for non-conductively interconnecting integrated circuits

Abstract

A method and apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules. Such systems provide lower cost, improved testability/repairability and greater density than conventional modular packaging techniques, such as printed circuit boards and multi-chip modules. The non-conductive interconnection technique of the invention can be applied to all levels in the packaging hierarchy, from bare semiconductor dies to complete functional sub-units. Numerous exemplary systems and applications are described.

Description

FIELD OF THE INVENTION [0001] Packaging Technologies [0002] The present invention relates generally to the field of electronic and microelectronic packaging and, more particularly, to a multichip package, a method for assembling, testing and repairing systems so packaged, and a method for communicating between circuits so packaged, via capacitive coupling. Of particular interest are digital systems, meaning systems which contain important constituents that operate according to the rules of multistate or binary logic. BACKGROUND OF THE INVENTION [0003] Electronic systems are usually implemented as hierarchical packages of components. Passive or active electronic elements, such as resistors and transistors, and their wiring are typically combined into memory or logic units, which are then combined into circuits and devices, which are combined into larger functional units, and so forth up to the level of a system. [0004] Each higher level of hierarchy grants the designer greater produc...

AI Technical Summary

Benefits of technology

[0088] Another object of the invention relates to a method and apparatus for reducing the cost of package engineering and manufacturing for modular electronic systems.

[008

Problems solved by technology

Inspection of the solder joints can be done with thermographic or radiographic techniques, but may be difficult otherwise.

“Chips-first” face-up wire-bonding of silicon dies to high density silicon, ceramic, or copper-polyimide modules is similar to conventional hybrid manufacturing technologies, and shares difficulties in rework and bonding yield.

The package is extremely dense, although heat dissipation can become limiting, but leads must still travel out to the edge and back to route to other die.

The package is extremely dense and conceptually trivial, but extremely difficult to manufacture.

However, as the size of a die approaches some economically and technologically feasible limit, the probability that randomly occurring manufacturing defects will produce an unacceptable die rises exponentially in a Poisson distribution.

Since slightly larger die yield at significantly lower rates, this so-called “surface-to-volume” (communication-to-computation) ratio severely constrains fabrication yield, hence cost per functioning die.

The need for multichip technologies arises in large part from this inability to produce arbitrarily large semiconductor dies with acceptable yield.

Practical limits on die size for a given technology force system designers to partition large digital systems among multiple dies.

Unfortunately, such partitioning dramatically impacts system performance since inter-die communication typically inflates packaging costs by tens to many hundreds of percent.

At present, customization generally requires a lengthy (circa six week) logic array masking process, unreliable laser fusing/breaking of wiring junctions, significant expense in microfabrication of wiring, macro-scale (e.g., wire-wrap) assemblages, lack of durability (e.g., hand-wired jury-rigs), or a combination of these.

The number of leads or number of chips within an area may inflate cost by a significant factor in many packaging technologies, such as those using wire-bonds.

Even if a technology avoids scaling as the number of leads or die, if it requires post-processing steps to form a package, as with solder bump conductive couples, it may still be expensive due to yield losses from handling, amortization of costly test/repair cycles, and of course operating and capital costs.

Runaway wiring density can in principle choke off the manufacturability of large high performance systems.

A further need for multi-chip technology arises from the cost and complexity of combining hybrid materials to exploit properties of each.

For instance, an arbitrarily large, cheap silicon CMOS chip would still lack the speed and optical properties of GaAs, while growing one material on the other is inherently more complicated than forming them separately.

A further need arises from the difficulty of package manufacture per se.

The engineering or manufacturing complexity, process requirements, and cost of the package approach or exceed those of the die, so the cost and turnaround time for the package can become as formidable as those of the die.

Despite the intensive research efforts of the past several years, present day MCM technologies still have significant problems in terms of cost, performance, design, manufacturability, reliability and reparability, as well as shortcomings with respect to the needs enumerated above.

Present MCM technologies require significant retooling and/or expensive reorientation of existing integrated circuit (“IC”) fabrication lines.

High volume is needed to realize cost advantages of MCM packaging, but re-implementing an existing production system (for which high volume demand already exists) to utilize MCM technology typically requires extensive system-wide redesign.

Accordingly, the relatively high up-front cost of MCM implementation discourages use of MCM technology for systems where large volume cannot be predicted a priori.

Reparability and die attach yield issues also arise with current MCM technology, principally because of the difficulty in die removal and replacement.

Testing the dies in the MCM before it is fully assembled (and paid for) typically accounts for tens of percent of the delivered MCM cost, due to the need for sacrificial test rigs or time-consuming intermediary connections as well as the cost of compensating for parasitics in order to test at operating speeds.

Making physical contact with microscopic probes or rigs of probes is slow, and exposes the probe points

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