System and method for testing system fault on integrated circuit board

Abstract

The invention relates to an accident detection system and method of SoC System on a chip, which comprises the following parts: strong detection circuit for complete integration chip; detection invitation mechanism whose circuit connects together with serial detection buses; parallel detection bus; IP (Intellectual Property) seed rim packaging chain circuit unit; clock controlling unit and IP seed selection decoding unit. The invitation detection mechanism consists of IP seed independent invitation detection mechanism and IP accident invitation detection mechanism between seeds. This invention adapts each present IP (DFT Design for Testability) method to detect circuit by system layer and IP seeds, which improves system accident percentage of coverage on the integration chip.

Description

technical field [0001] The invention relates to an integrated circuit fault testing system and method, in particular to a fault testing system and method applied to an integrated circuit system on a chip (SoC System on a Chip). Background technique [0002] Based on IP (Intellectual Property) multiplexing technology, the design scale and implementation function of integrated circuits have undergone a sudden change, from the original dedicated function VLSI Very Large Scale Integration Circuit (VLSI Very Large Scale Integration Circuit) to the current system-on-chip. However, with the increase in the scale and design complexity of integrated circuit SoCs, the originally difficult test problems are becoming more and more severe. If the testing problem of the integrated circuit system on chip cannot be effectively solved, it will become a major bottleneck in the development of the integrated circuit system on chip. [0003] Integrated circuit system-on-chip designed and built ...

AI Technical Summary

Problems solved by technology

These test methods all exist: different circuit structure characteristics in the IP core layer, IP cores use the same DFT method, and there are no test links for connection faults between IP cores, which in turn leads to integrated circuit system-on-chip fault test overhead and fault coverage. Rate indicators are difficult to be effectively controlled and improved

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