System and method for testing system fault on integrated circuit board

A system-on-chip and integrated circuit technology, which is applied in the direction of electronic circuit testing, measuring electronics, and measuring devices, etc., can solve problems such as the difficulty in effectively controlling and improving the fault coverage index of the integrated circuit system-on-chip chip fault test, and achieve test The search mechanism is simple, the test overhead is reasonable, and the fault coverage rate is improved

Inactive Publication Date: 2006-02-15
SHANGHAI UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

These test methods all exist: different circuit structure characteristics in the IP core layer, IP cores use the same DFT method, and there are no test links for connection faults bet

Method used

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  • System and method for testing system fault on integrated circuit board
  • System and method for testing system fault on integrated circuit board
  • System and method for testing system fault on integrated circuit board

Examples

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Embodiment Construction

[0031] A preferred embodiment of the present invention is: referring to Fig. 1, Fig. 2 and Fig. 3, it includes a circuit added to improve the testability of the integrated circuit system on chip and a test seeking mechanism based on the operation of the circuit. Its circuit is composed of IP core serial test bus 1, parallel test bus 2, IP (Intellectual Property) core edge packaging unit link 3, clock control unit 4 and IP core selection decoding unit 5; its test search mechanism is composed of IP core It consists of an independent test search mechanism 6 and an IP core inter-core connection fault test search mechanism 7.

[0032] This circuit structure is: referring to Fig. 1, the serial test bus 1 has the input and output pins WSI, WSO of the external scan link, and the edge packaging unit link 3 connected to each IP core by the chip output; the parallel test bus 2 has a group The test bus signal input pin TBI and a group of test bus signal output pins TBO are connected to th...

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Abstract

The invention relates to an accident detection system and method of SoC System on a chip, which comprises the following parts: strong detection circuit for complete integration chip; detection invitation mechanism whose circuit connects together with serial detection buses; parallel detection bus; IP (Intellectual Property) seed rim packaging chain circuit unit; clock controlling unit and IP seed selection decoding unit. The invitation detection mechanism consists of IP seed independent invitation detection mechanism and IP accident invitation detection mechanism between seeds. This invention adapts each present IP (DFT Design for Testability) method to detect circuit by system layer and IP seeds, which improves system accident percentage of coverage on the integration chip.

Description

technical field [0001] The invention relates to an integrated circuit fault testing system and method, in particular to a fault testing system and method applied to an integrated circuit system on a chip (SoC System on a Chip). Background technique [0002] Based on IP (Intellectual Property) multiplexing technology, the design scale and implementation function of integrated circuits have undergone a sudden change, from the original dedicated function VLSI Very Large Scale Integration Circuit (VLSI Very Large Scale Integration Circuit) to the current system-on-chip. However, with the increase in the scale and design complexity of integrated circuit SoCs, the originally difficult test problems are becoming more and more severe. If the testing problem of the integrated circuit system on chip cannot be effectively solved, it will become a major bottleneck in the development of the integrated circuit system on chip. [0003] Integrated circuit system-on-chip designed and built ...

Claims

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Application Information

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IPC IPC(8): G01R31/28G01R31/00
Inventor 张金艺李娇盛强任小军陈文威
Owner SHANGHAI UNIV
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