32results about How to "Reduce test power consumption" patented technology

The invention relates to the field of an integrated circuit test, and discloses a test graphic generator of an integrated circuit and a test method thereof. The test graphic generator comprises a reconfigurable linear feedback shift register of cyclic code with single bit change, a liner feedback shift register based on a primitive polynomial and a two-dimensional exclusive or gate array; compared with the traditional test graphic generator, the test graphic generator has less hardware overhead, few quantity of repeated test graphics, short test time, uniform distribution of generated test graphics, and can obtain higher fault coverage rate; and the generated single jump test sequence reduces the conversion times of a tested circuit input end, thus greatly reducing the test power consumption of the tested integrated circuit.

The invention is applied to the technical field of optics, and provides a distance measuring method and a depth camera. The distance measuring method comprises the following steps: transmitting an optical signal to an object to be measured; receiving the optical signal reflected by the object to be measure through a receiving module, wherein the receiving module comprises a plurality of signal collecting units, the timing sequences of the plurality of signal collecting units are different, and each signal collecting unit has at least two sets of collection signals with different frequencies inone exposure time; and calculating the flight time of the optical signal. By setting a plurality of taps in the depth camera, and controlling the collecting timing sequences of the plurality of collecting units through the control module, each tap has at least two sets of collection signals with different frequencies in one exposure time; therefore, the contradiction of in test scheme in the prior art that the pulse width is proportional to the test distance and power consumption and is negatively correlated with the test accuracy is got rid of, and the measurement distance is no longer limited by the pulse width; therefore, lower test power consumption and higher test accuracy is maintained while achieving a farther test distance.

The invention discloses a scanning subchain type test structure capable of conforming to boundary scan standards. The scanning subchain type test structure comprises a vector configuration module and a response aggregation module, wherein the vector configuration module is used for conducting reconfiguration to divide a test signal into a plurality of parallel boundary scanning subchains to be connected with the response aggregation module, all data output ends of the vector configuration module are connected with the data input ends of all the boundary scanning subchains respectively, and a test response output by the output end of the response aggregation module is connected with a TDI port of a boundary scan test controller. The invention further discloses a scanning subchain type test method capable of conforming to the boundary scan standards and application of the scanning subchain type test structure and method in diagnosis of faults of a tested circuit board. According to the scanning subchain type test structure and method, the scanning subchain type test structure and method can conform to the standards, the requirements of the scanning subchain type test structure can be met, the position passing rate in the shifting process of a boundary scan test is lowered, and therefore the power consumption of the boundary scanning test is lowered.

The invention discloses a low-power consumption boundary scanning test method, belongs to the field of SOC boundary scanning test, and aims at solving the problem that the existing low-power consumption boundary scanning test methods are at the cost of sacrificing the fault coverage rate so that the test results are influenced. According to the method, the output end of each chip on an SOC is connected with a BSLC scanning unit; the SI ends and SO ends of every two adjacent boundary scanning units in n BSLC scanning units are sequentially connected in series to form an input boundary scanningchain which is used for sending test excitations to a function path; the input end of each chip is connected with a BSCC scanning unit; the SI ends and SO ends of every two adjacent boundary scanningunits in m BSCC scanning units are sequentially connected in series to form an output boundary scanning chain which is used for capturing and moving test responses; and when each bit of test data is moved in, the state of a trigger on the whole scanning chain is switched for less than twice, so that the test power consumption is greatly decreased.

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

The invention provides a chip testing method and device, a chip testing machine and a storage medium, and relates to the technical field of chip testing, and the method comprises the steps: determining a target register of a target enabling end of a clock gating unit in a chip; obtaining a target scan chain based on a plurality of target register combinations; generating a target enable signal through the set values of a plurality of target registers on the target scan chain; and controlling a target clock gating unit corresponding to a target enabling end in the clock gating units to be opened or closed through the target enabling signal. On the basis of generating the target scan chain, the clock gating unit can be controlled to be opened and closed in the chip scan test mode by controlling the value of the register, so that the control difficulty of the clock gating unit is reduced, the opening proportion of the clock gating unit is effectively controlled, the number of test vectors is reduced, the test coverage rate is improved, and the test efficiency is improved. Therefore, the test power consumption during the chip scanning test is reduced, and the test cost is reduced.

The invention discloses a controllable Chiplet serial test circuit, and belongs to the technical field of testing or measuring of semiconductor devices in the manufacturing or processing process. The test circuit comprises a master control test module, a slave control test module, a clock control module and an output module, the master control test module is composed of a test access port module, a segment insertion bit module and a test data register module, and a test control signal is generated through the master control test module; the slave control test modules respectively control test input signals of the slave control core particles after receiving the test control signals. Meanwhile, the test control signal is input to the clock control module to obtain a clock signal of the slave control core particle. The output signal of the test output module is determined by the test control signal. According to the test circuit, an external test port is used for directly controlling an internal test signal of the multi-core-particle integrated circuit, core particle test selection and final test output are realized, and effectiveness and independence of each core particle test are ensured.

The invention relates to a selective generation method for state vectors of a parallel folding counter and a hardware circuit for the selective generation method. The selective generation method is characterized by comprising the following steps of establishing a logical relation among an initial inversion control vector, a folding distance and a corresponding inversion control vector; realizing selective bit replacement on the initial inversion control vector through the decoded output of the folding distance to generate the inversion control vector corresponding to the folding distance; then, performing bitwise exclusive-or operation on the generated inversion control vector and folding seeding vectors in sequence, therefore realizing the selective generation of the state vectors of the folding counter. According to the selective generation method disclosed by the invention, for the given folding seeding vectors and a given folding distance value, the state vector corresponding to the folding distance can be directly generated, and therefore the generation efficiency of deterministic BIST (build-in self-test) test vectors is obviously increased, the generation of redundant state vectors is avoided, and the test time and the test power dissipation of the circuit are reduced.

The invention discloses a gallium nitride device reliability testing device and a testing method. The device comprises a load resistor, a load capacitor and a first semiconductor switching device, wherein one end of the load resistor is connected to a direct current power supply, and the other end of the load resistor is connected to a drain electrode of the first semiconductor switching device; the source electrode of the first semiconductor switching device is respectively connected to the drain electrode of the gallium nitride device to be tested and one end of the load capacitor, the other end of the load capacitor is connected to the direct current power supply, and the source electrode of the gallium nitride device to be tested is grounded; the grid electrode of the first semiconductor switching device is connected to the first pulse generator, and the grid electrode of the gallium nitride device to be tested is connected to the second pulse generator. By adopting the device and the testing method provided by the invention, the system testing power consumption is greatly reduced, the test can be accelerated in a single wide range, and the requirements of low power consumption, high flexibility, multi-dimension and large-batch test of the gallium nitride device are met.

The invention aims to provide the test method and device of the integrated circuit chip and the storage medium, so that the test power consumption of the integrated circuit chip can be effectively reduced; in order to achieve the purpose, the testing method and device of the integrated circuit chip and the storage medium are provided, in the testing process, the testing device uses data of all registers as testing signals to be provided for all circuit modules of the integrated circuit chip through the initial shifting action, and therefore the testing accuracy of the integrated circuit chip is improved. And then obtaining output data of each logic circuit in each register through a capture action. Then, the shift operation and the capture operation are repeated, and the test of each logic circuit is performed by comparing the obtained output data of each circuit module with an expected value thereof.

The invention discloses a fault injection method based on dual-port SRAM (system random access memory), which comprises the following steps:A arranging a first code selector behind a coder of a first port of the SRAM; arranging a second code selector behind a coder of a second port; and globally applying an external control signal TEST to the first code selector and the second code selector of the SRAM. The in-chip fault injection method disclosed by the invention can implement control by one control signal outside the chip without introducing any other external injection signal, only occupies small internal chip area, and can quickly implement the fault injection test. Meanwhile, since the method is only logically equivalent fault injection instead of direct error injection, thereby lowering the test power consumption. Besides, the test operation is simple and quick, and the method has the advantages of low cost and high test coverage rate.

The invention discloses a low power consumption LFSR reseeding test compression method facing scanning design structures. Thus, problems of excessive high test power consumption brought by a traditional LFSR reseeding technology can be solved. Based on an optimized coding algorithm of a test cube, the method can combine with any LFSR reseeding scheme, and be applied to industrial grade super-large-scale integrated circuits and the built-in self-testing of system on chips and functional verification thereof. The basic thinking of the method is as follows: random filling can be performed on don't care bits in the test cube during a LFSR reseeding process, which can trigger excessive high switch switching rates and test power consumption. The method can enhance the logic consistency between adjacent bits in the test cube by optimizing codes, so that test power consumption can be effectively reduced; and seed vector solving difficulty can be reduced by reducing the number of determined bits in the test cube and the number of state equations, so that test data compression rates can be effectively enhanced, and the challenges of testing storage resources can be alleviated.