Scan sub-chain type test structure and test method in compliance with boundary scan standard

Abstract

The invention discloses a scan sub-chain type test structure conforming to the boundary scan standard, including a vector configuration module and a response aggregation module. The vector configuration module reconfigures the test signal into multiple parallel boundary scan sub-chains and is connected to the response aggregation module. Each data output end of the vector configuration module is connected to the data input end of each boundary scan sub-chain, the data output end of each boundary scan sub-chain is connected to the data input end of the response aggregation module, and the test response output by the output end of the response aggregation module Connects to the TDI port of the boundary scan test controller. The invention simultaneously discloses a scan sub-chain type test method conforming to the boundary scan standard, and the application of the scan sub-chain type test structure and the test method in diagnosing the fault of the tested circuit board. The invention can not only meet the standard but also satisfy the requirement of the scan sub-chain test structure, reduce the bit passing rate in the shifting process of the boundary scan test, and further reduce the power consumption of the boundary scan test.

Description

technical field [0001] The invention relates to boundary scan, in particular to a scan sub-chain type test structure and test method conforming to the boundary scan test IEEE1149.1 standard. Background technique [0002] Presently known boundary scan technology all adopts single link mode serial test, and its test structure is mainly to form daisy chain in series between each boundary scan device on the single circuit board, and its test method comprises the following steps: (1) according to the circuit The netlist generates test vectors; (2) loads the test vectors to the scan chain through the test data input (Test Data Input, TDI); (3) reads out the test response and performs fault diagnosis through the test data output (Test Data Output, TDO). This method can realize the detection of integrated circuit faults, but due to the long scan chain, the power consumption of the test is high, which brings unnecessary troubles to the test, such as failing to pass the test, or even ...

AI Technical Summary

Problems solved by technology

This method can realize the detection of integrated circuit faults, but due to the long scan chain, the power consumption of the test is high, which brings unnecessary troubles to the test, such as failing to pass the test, or even causing the chip to be burned due to excessive temperature, etc.

The more common methods to reduce test power consumption include reducing test frequency, modifying test structure and test vector, etc., but these methods will increase the test cost, such as increasing the test cycle, etc.

During the test, due to the presence of many level transitions, the test power consumption increases rapidly

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