1567results about How to "High product yield" patented technology

The invention provides variant CDRs comprising highly restricted amino acid sequence diversity. These polypeptides provide a flexible and simple source of sequence diversity that can be used as a source for identifying novel antigen binding polypeptides. The invention also provides these polypeptides as fusion polypeptides to heterologous polypeptides such as at least a portion of phage or viral coat proteins, tags and linkers. Libraries comprising a plurality of these polypeptides are also provided. In addition, methods of and compositions for generating and using these polypeptides and libraries are provided.

The invention provides variant hypervariable regions comprising selected amino acid sequence diversity. Libraries comprising a plurality of these polypeptides are also provided. In addition, methods of and compositions for generating and using these polypeptides and libraries are provided.

A high-performance liquid crystal display device is provided that can be manufactured at a low cost and a high production yield. In this liquid crystal display device, a liquid crystal composition comprising liquid crystal molecules and a polymerizable compound that can be polymerized by ultraviolet rays or by a combination of ultraviolet rays and heat is disposed between a pair of substrates; the polymerizable compound is polymerized, forming a liquid crystal layer, by an operation including irradiation of ultraviolet rays that do not contain wavelength components of not higher than 313 nm; and uneven portions are installed on the liquid crystal layer contacting surface, or a slit pattern is installed in an electrode, or uneven portions are installed on the liquid crystal layer contacting surface, and a slit pattern is installed in the electrode.

A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Methods and systems for evaluating and controlling a lithography process are provided. For example, a method for reducing within wafer variation of a critical metric of a lithography process may include measuring at least one property of a resist disposed upon a wafer during the lithography process. A critical metric of a lithography process may include, but may not be limited to, a critical dimension of a feature formed during the lithography process. The method may also include altering at least one parameter of a process module configured to perform a step of the lithography process to reduce within wafer variation of the critical metric. The parameter of the process module may be altered in response to at least the one measured property of the resist.

A thin film solar cell includes: a transparent conductive film arranged on a translucent insulating substrate; first and second separation trenches orthogonal to each other on the translucent insulating substrate and separating the transparent conductive film; and a first opening trench parallel to the first separation trench and second opening trenches parallel to said second separation trench, orthogonal to each other on the translucent insulating substrate; wherein solar cells formed on the translucent insulating substrate are arranged at adjacent positions with said first opening trench positioned therebetween and at adjacent positions with said second opening trench positioned therebetween; pairs of said solar cells adjacent to each other with said first opening trench positioned therebetween are electrically connected, and among pairs of solar cells positioned adjacent to each other with the second opening trench in between, some are electrically connected to each other, and others are electrically insulated from each other. Method of manufacturing the thin film solar cell is also provided.

A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.

The present invention provides a method of producing pristine or non-oxidized nano graphene platelets (NGPs) that are highly conductive. The method comprises: (a) providing a pristine graphitic material comprising at least a graphite crystallite having at least a graphene plane and an edge surface; (b) dispersing multiple particles of the pristine graphitic material in a liquid medium containing therein no surfactant to produce a suspension, wherein the multiple particles in the liquid have a concentration greater than 0.1 mg/mL and the liquid medium is characterized by having a surface tension that enables wetting of the liquid on a graphene plane exhibiting a contact angle less than 90 degrees; and (c) exposing the suspension to direct ultrasonication at a sufficient energy or intensity level for a sufficient length of time to produce the NGPs. Pristine NGPs can be used as a conductive additive in transparent electrodes for solar cells or flat panel displays (e.g., to replace expensive indium-tin oxide), battery and supercapacitor electrodes, and nanocomposites for electromagnetic wave interference (EMI) shielding, static charge dissipation, and fuel cell bipolar plate applications.

A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields.

An electron source include a first cathode electrode disposed over a substrate and terminated to provide electrons; an emitter layer disposed over the cathode electrode and formed from one or plurality vertically aligned and mono-dispersed nano-structures that are truncated to the same length, embedded in a solid matrix and protruding above the surface for emitting electrons; an insulator disposed over the emitter layer and having one or plurality of apertures, each is self-aligned with and exposes one nano-structure in the emitter layer; and a second gate electrode disposed over the insulator, having one or plurality of apertures self-aligned with the apertures in the insulator and terminated to extract electrons from the exposed nano-structures through the apertures. The gate aperture is substantially less than one micrometer and the gated nano-structures can have a density on the order of 10⁸/cm². Such an electron source can be modulated with an extra low voltage, emits electrons with high current density and high uniformity, and operates with high energy-efficiency and long lifetime.

A multi-wavelength optical transmitting module includes a housing, an optical output block, an optical transmitting block, and an optical multiplexer (MUX) block. The housing has a first coupling hole and a second coupling hole respectively formed in opposite surfaces thereof. The optical output block is coupled to the first coupling hole of the housing, is connected to an optical signal connector, and includes a first lens. The optical transmitting block is coupled to the second coupling hole of the housing and is connected to an electrical signal connector. In addition, the optical transmitting block includes a plurality of transmitting devices which respectively output light having different wavelengths and are arranged parallel to the optical output block, and a plurality of second lenses which are arranged on a light output side of the transmitting devices to correspond respectively to the transmitting devices. The optical multiplexer (MUX) block is disposed within the housing, multiplexes optical signals of multiple wavelengths, which were output from the transmitting devices and passed through the second is lenses, and transmits the multiplexed optical signals to the optical output block.

Disclosed herein is a biosensor for measuring analyte in a fluid that comprises a substrate layer having disposed thereon at least one each of an electrode, cathode, anode, and a novel spacer material. The spacer material according to the present disclosure comprises a heat sealable organic layer that covers at least a portion of the anode and defines at least one edge of the anode, wherein the spacer material has at least one hole punched through it and defines a cavity or well for accepting chemistry. Also disclosed is a method of making such biosensors.

The disclosed invention relates to a process for conducting an equilibrium limited chemical reaction in a microchannel reactor. The process involves the use of active heat exchange and is suitable for conducting exothermic and endothermic reactions. The process is particularly suitable for synthesizing methanol and dimethyl ether.

The present invention relates to a method for synthesizing an RNA molecule of a given sequence, comprising the step of determining the fraction (1) for each of the four nucleotides G, A, C and U in said RNA molecule, and the step of synthesizing said RNA molecule by in vitro transcription in a sequence-optimized reaction mix, wherein said sequence-optimized reaction mix comprises the four ribonucleoside triphosphates GTP, ATP, CTP and UTP, wherein the fraction (2) of each of the four ribonucleoside triphosphates in the sequence-optimized reaction mix corresponds to the fraction (1) of the respective nucleotide in said RNA molecule, a buffer, a DNA template, and an RNA polymerase. Further, the present invention relates to a bioreactor (1) for synthesizing RNA molecules of a given sequence, the bioreactor (1) having a reaction module (2) for carrying out in vitro RNA transcription reactions in a sequence-optimized reaction mix, a capture module (3) for temporarily capturing the transcribed RNA molecules, and a control module (4) for controlling the infeed of components of the sequence-optimized reaction mix into the reaction module (2), wherein the reaction module (2) comprises a filtration membrane (21) for separating nucleotides from the reaction mix, and the control of the infeed of components of the sequence-optimized reaction mix by the control module (4) is based on a measured concentration of separated nucleotides.

A method for manufacturing a semiconductor device wherein both the threshold voltages of an N-type MISFET and a P-type MISFET are low, device can be easily manufactured at a lower cost and a higher product yield, and the reliability of the gate insulation film is higher. The gate insulation film is formed on the surface of a silicon substrate 1 in N-type MISFET forming region and the P-type MISFET forming region, and metal gates 4 and 5 are provided thereon. The metal gate 4 is made from a TiCoN film, and the work function thereof is set at 4.0 to 4.8 eV suited to the gate electrode material of the N-type MISFET. The metal gate 5 is formed from a portion of the TiCoN film by ion-implantation of oxygen into the TiCoN film configuring the gate electrode 4 at a dosage of 1013 to 1014 (ions/cm2) to raise the work function by around 0.2 to 0.8 eV.

A quad flat non-lead (QFN) package at least comprises a die, a lead frame and a molding compound. The lead frame comprises a plurality of L-shaped leads for electrically connecting the die. Two pre-plated conductive layers, formed on a bottom portion and a top portion of each L-shaped lead, are exposed to a bottom surface and a top surface of the package, respectively. The molding compound is formed for encapsulating the die and the L-shaped leads.

A substrate structure with embedded chips of a semiconductor package and a method for fabricating the same are proposed. First of all, a carrier structure having a first carrier plate and a second carrier plate being directly formed on the first carrier plate is provided. The second carrier plate is provided with at least an opening. Then, a non-active surface of at least a semiconductor chip is mounted onto the first carrier plate and embedded in the opening of the second carrier plate. A dielectric layer is subsequently formed on a surface of the chip and the second carrier plate, and the material of the dielectric layer is filled in the opening of the second carrier plate. Afterwards, a plurality of vias is formed penetrating through the dielectric layer to expose conductive pads located on an active surface of the chip. A circuit layer and conductive vias are then respectively formed on a surface and penetrating through the dielectric layer, such that the circuit layer can be electrically connected to the conductive pad located on the chip by the means of the conductive via. Finally, conductive elements are provided on a surface of the circuit layer, so that the semiconductor chip embedded in the carrier plate can be electrically connected to an external device.

A radiation detection apparatus including a sensor panel, having a photoreceiving unit constituted of plural photoelectric converting elements two-dimensionally arranged on a substrate and electrical connecting portions provided in an external portion of the photoreceiving unit and electrically connected to the photoelectric converting elements of respective rows or columns of the photoreceiving unit, a phosphor layer provided at least on the photoreceiving unit for converting a radiation into a light detectable by the photoelectric converting element, and a phosphor protective member covering the phosphor layer and in contact with the sensor panel, characterized in that the phosphor protective member includes a frame member provided between the phosphor layer and the electric connecting portion on the sensor panel, and a phosphor protective layer covering an upper surface of the phosphor layer and provided in close contact with an upper surface of the frame member. This configuration allows to prevent a discharge of an electrostatic charge accumulated on the sensor panel, thereby providing a stable radiation detection apparatus with a high production yield.