11 results about "Extra-low voltage" patented technology

Disclosed in the present invention is a floating inverter amplifier based on capacitor stacking, which boosts a power supply of the floating inverter amplifier to 2 times VDD by means of the capacitor stacking; under such condition, a transistor in the inverter may be better turned on, and a cascode structure can be applied to an inverting amplifier operating at a low power supply voltage. Furthermore, an ADC system employing the floating inverter amplifier of the present invention can process an input signal with a common-mode voltage of VDD and an amplitude up to 2 times VDD, which effectively addresses a problem of a reduced input signal amplitude under an ultra-low voltage, thereby increasing a signal-to-noise ratio of the system.

An ideal diode circuit comprises a transistor, a low-voltage reference module, an ultra-low-voltage power supply module and a voltage drop detection circuit, the low-voltage reference module provides three different reference voltages and bias voltages, the ultra-low-voltage power supply module adopts N charge pumps in series to step up the voltage drop of the transistor, and outputs a control voltage Vcp to supply power for the internal circuit of the ideal diode, the voltage drop detection circuit compares the voltage drop of the transistor with the three reference voltages through comparators respectively, controls the opening or closing of the charge pump of the ultra-low-voltage power supply module, and realizes adaptive variable amplification multiple step-up of the voltage drop VIN-VOUT. The ideal diode control technology provided by the application utilizes variable charge pump amplification multiple, provides adaptive adjustment of the amplified voltage, and meets the continuous and stable operation of the circuit in the working voltage range of the ideal diode.

This invention relates to the field of circuit hardening technology, and provides a voltage-controlled oscillator (VCO) circuit and phase-locked loop (PLL) circuit that are resistant to single-event transients. Addressing the issue that traditional three-mode relaxation oscillator (VCO) circuits are unsuitable for low-voltage conditions, especially when the power supply voltage drops to around 0.8V, this invention employs six oscillation branches coupled into three large oscillation loop circuits to improve loop gain. Furthermore, by combining bias circuits, comparators, and voting circuits for each path, the problem of increasing nonlinearity is avoided. This achieves a combination of large oscillation loops, bias circuits, and a three-mode VCO architecture, resulting in a VCO circuit that maintains high-frequency stable operation under ultra-low voltage conditions such as 0.8V, thus achieving a single-event transient resistance effect, especially at low voltages of 0.8V.

The invention provides a polar region natural temperature difference-based TEG power generation circuit, a working method and a layout method, relates to the technical field of temperature difference power generation, is adaptive to low temperature difference and field unattended scenes, and supplies energy to a 5V / 0.1 W monitoring acquisition module. The circuit comprises a TEG thermoelectric power generation sheet, an ultra-low voltage energy acquisition module, an energy storage module, a voltage equalization circuit, a control module, a load switch module, a low temperature preheating module and a monitoring acquisition load which are electrically connected. Micro-temperature-difference electric energy efficient collection is achieved through an ultra-low voltage starting chip and a high-turn-ratio transformer, a low-temperature low-leakage series super capacitor is adopted for energy storage, pulse type work and a low-temperature preheating strategy are combined, and a thermoelectric collaborative PCB layout is matched, so that the problem that low-power collection cannot stably supply energy to a high-power load under the micro-temperature difference is solved; and the system can be widely applied to unattended environment monitoring scenes of polar regions, high altitudes and the like.

The invention discloses an ultra-low power consumption body-driven four-stage differential operation transconductance amplifier, which belongs to the technical field of CMOS (Complementary Metal Oxide Semiconductor) analog integrated circuits, and comprises a biasing circuit, a body-driven differential input circuit, a composite differential amplification circuit, a frequency compensation circuit and a common-mode feedback circuit. The bias circuit provides stable bias under the ultra-low voltage of 0.3 V; the body-driven differential input circuit takes a PMOS tube body end as a differential signal input end, and improves equivalent transconductance in combination with a cross positive feedback structure; the composite differential amplification circuit realizes signal multi-stage amplification and rail-to-rail output through a two-stage differential common-source amplification unit and a feedforward AB type output unit; the frequency compensation circuit optimizes the frequency stability in a mode of combining a Miller capacitor and an RC (Resistance-Capacitance) compensation network; and the common-mode feedback circuit stably outputs a common-mode level. The amplifier is suitable for ultra-low power consumption application scenes such as implantable medical electronics and wearable equipment.

The present disclosure relates to a portable Extra-Low Voltage (ELV) class-II lubrication device comprising: at least one class-II power supply; at least one electric motor controller powered by the at least one power supply; at least one electric motor controlled by the at least one motor controller; at least one pump activated by the at least one electric motor and connected to at least one lubricant container, the pump configured to pump a lubricant from the at least one container to at least one target to be lubricated, wherein an output voltage of the at least one power supply and an output voltage of the at least one motor controller and an operating voltage of the at least one motor is equal to or less than 50 Volts AC or 120 Volts DC.

A memory array includes a write assist circuit that helps ensure that write operations can be effectively and efficiently performed in spite of low voltage supply levels. The write assist circuit includes a negative voltage generator that generates a negative voltage during write operations and applies the negative voltage to a bitline coupled to a selected memory cell. The negative voltage helps ensure that data is quickly and properly written to the memory cell. The write assist circuit also includes a leakage control circuit that helps reduce leakages associated with generation of the negative voltage by applying the negative voltage to other portions of the memory array in order to reduce leakage currents.

The utility model discloses a super capacitor management unit capable of self-starting under ultra-low voltage, and belongs to the technical field of super capacitor management. Comprising an acquisition equalization circuit, a control communication circuit, a power supply circuit and a boost circuit. The booster circuit is connected with the positive electrode and the negative electrode of the super capacitor and is used for taking power from the super capacitor and inputting the power into the power supply circuit after boosting; the power supply circuit takes power from the booster circuit and inputs the power to the acquisition equalization circuit and the control communication circuit to provide working power for the acquisition equalization circuit and the control communication circuit; one end of the acquisition equalization circuit is connected with the super capacitor, and the other end is connected with the control communication circuit. According to the utility model, the booster circuit is additionally arranged in the CMU topology, so that the Vthreshold can be greatly reduced, the monitoring blind area when the super-capacitor module is started from 0V is shortened, and the effect is more obvious under the scene that a plurality of super-capacitor modules are connected in series for use.

An auxiliary power supply for an energy storage rack of a high-voltage DC system. The power supply has at least one AC power supply branch with input terminals, transfer terminals and a low voltage transformer. The low voltage transformer has an input branch configured for receiving AC electrical power from the input terminals, a transfer branch configured for transferring the AC electrical power to the transfer terminals, and s a supply branch configured for transforming the received AC electrical power to a lower voltage in extra low voltage range for supplying a control unit. The power supply also has at least one DC power supply branch that includes an LV DC power source configured for supplying DC electrical power to the control unit. Also an energy storage rack and a energy storage system.

An ideal diode circuit comprises a transistor, a low-voltage reference module, an ultra-low-voltage power supply module and a voltage drop detection circuit, the low-voltage reference module provides three different reference voltages and bias voltages, and the ultra-low-voltage power supply module boosts the voltage drop of the transistor by adopting N charge pumps connected in series and outputs a control voltage Vcp, and the voltage drop detection circuit is used for respectively comparing the voltage drop of the transistor with three reference voltages through a comparator, and controlling the opening or closing of a charge pump of the ultra-low voltage power supply module, so that the self-adaptive variable amplification factor boosting of the voltage drop VIN-VOUT is realized. According to the invention, a novel ideal diode control technology is provided, and a variable charge pump amplification factor is utilized to provide an adaptively adjusted amplification voltage, so that a circuit can continuously and stably work within an ideal diode working voltage range.

Disclosed herein a static random-access memory (SRAM) circuits designed to operate reliably in scenarios where the memory array supply voltage (VDDMA) significantly exceeds the peripheral circuit supply voltage (VDDMP). Various configurations of pre-charge and pre-charge assist circuits are disclosed, each aimed at preventing unintended state changes in bitcells during read operations. These circuits employ techniques such as charge transfer from a higher voltage domain, capacitive coupling, and sense amplifier decoupling to boost bitline voltages above VDDMP during critical read phases. This enables stable SRAM operation with a large voltage differential between VDDMA and VDDMP, facilitating improvements in both performance and power efficiency.