15 results about "Self-aligned gate" patented technology

Techniques are provided herein to form semiconductor devices that include one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors with a gate cut that extends through at least an entire thickness of the gate structure and includes dielectric material. The gate cut includes a hybrid design that is formed in two parts. A first part of the gate cut is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second part of the gate cut is formed over the first part of the gate cut and is integrated with spacer structures formed on the sidewalls of a sacrificial gate that extends over the adjacent fins.

A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source / drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

Semiconductor devices with self-aligned gate isolation and wrap around source / drain contacts are provided. In one aspect, a semiconductor device includes: at least a first FET (FET1) and a second FET (FET2), adjacent to one another on a wafer; a dielectric bar between gates of the FET1 and the FET2, and between source / drain regions of the FET1 and the FET2; and wrap around source / drain contacts that at least partially surround the source / drain regions of the FET1 and the FET2. A shallow trench isolation (STI) region can be present between the FET1 and the FET2 and the dielectric bar can be centered over, and directly contact the STI region. Portions of the dielectric bar between the gates and between the source / drain regions can have a height H1 and H2, respectively, where H1>H2. A method of fabricating the present semiconductor device is also provided.

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Embodiments of this disclosure relate to a split-gate channel MOS transistor having a self-aligned gate region and a body region. A method for fabricating an integrated device having at least one MOS transistor integrated on a die of semiconductor material is proposed. The method includes forming one or more gate trenches having corresponding field plates and gate regions. The body region is formed by selectively implanting dopant along one or more implantation directions inclined relative to the front surface of the die. Furthermore, corresponding integrated devices and systems including such integrated devices are proposed.

Self-aligned gate isolation / cutting techniques for multigate devices are disclosed herein. An exemplary multigate device includes a first gate having a gate stack that surrounds a semiconductor layer. The first gate is disposed between a first gate isolation wall and a second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, and the first sidewall is formed by the gate dielectric and the gate electrode. A gate endcap is disposed on the first sidewall. A gate helmet is disposed over the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate helmet. A gate contact is disposed on the first gate. The gate contact extends over the first gate isolation wall and connects the first gate to a second gate.

Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

A microelectronic structure that includes a first nanosheet transistor that includes a first source / drain and a second nanosheet transistor that includes a second source / drain. A first frontside source / drain contact that includes a horizontal section and a protrusion section. The horizontal section of the first frontside source / drain contact is in contact with the flat horizontal frontside surface of the first source / drain. The protrusion section of the first frontside source / drain contact is in contact with the at least one inclined side surface of the first source / drain. A second frontside source / drain contact that includes a horizontal section and at least one protrusion section. The horizontal section of the second frontside source / drain contact is in contact with the flat horizontal frontside surface of the second source / drain. The at least one protrusion section of the second frontside source / drain contact is in contact with the at least one inclined side surface of the second source / drain.

The invention relates to a self-aligned gate cut with a hybrid architecture. Techniques are provided herein for forming a semiconductor device that includes one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure surrounding or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors having a gate cut-out extending through at least an entire thickness of the gate structure and including a dielectric material. The gate cut-out includes a hybrid design formed in two portions. A first portion of the gate cut-out is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second portion of the gate cut-out is formed over the first portion of the gate cut-out and integrated with a spacer structure formed on sidewalls of the sacrificial gate extending over adjacent fins.

A semiconductor device is provided that includes a self-aligned gate cut structure electrically isolating, at least in part, a gate structure of a first transistor from a gate structure of a second transistor. The distance from a semiconductor channel region of the first transistor to the self-aligned gate cut structure is the same as the distance from a semiconductor channel region of the second transistor to the self-aligned gate cut structure.