30 results about "Self-aligned gate" patented technology

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

Techniques are provided herein to form semiconductor devices that include one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors with a gate cut that extends through at least an entire thickness of the gate structure and includes dielectric material. The gate cut includes a hybrid design that is formed in two parts. A first part of the gate cut is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second part of the gate cut is formed over the first part of the gate cut and is integrated with spacer structures formed on the sidewalls of a sacrificial gate that extends over the adjacent fins.

A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source / drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

A method of forming a semiconductor structure includes forming fins over a substrate, forming shallow trench isolation regions around the fins, and forming nanosheet stacks that provide channels for nanosheet field effect transistors. The method also includes forming a channel protection liner over sidewalls and a portion of a top surface of a first nanosheet stack formed on a first fin, the channel protection liner further formed over a portion of the shallow trench isolation regions extending from the sidewalls of the first nanosheet stack to a second nanosheet stack formed on a second fin. The method also includes forming a gate stack around exposed portions of the nanosheet stacks, forming asymmetric self-aligned gate isolation structures over the channel protection liner, and forming symmetric self-aligned gate isolation structures over a portion of the shallow trench isolation regions between a third fin and a fourth fin.

One embodiment of the invention provides a method for fabricating a self-aligned gate structure comprising forming at least one first trench having a first width and at least one second trench having a second width in a gate structure comprising a first metallic gate layer. The first width is smaller than the second width. The method comprises depositing at least one conformal dielectric layer on the first metallic gate layer. The dielectric layer completely fills the first trench and partially fills the second trench, such that a portion of the second trench is unfilled. The method comprises depositing a conformal second metallic gate layer on the dielectric layer. The second metallic gate layer fills the unfilled portion of the second trench. The method comprises removing portions of the second metallic gate layer to expose the dielectric layer. Remaining portions of the second metallic gate layer include self-aligned metallic gate electrodes.

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

Disclosed are apparatuses including a transistor cell and methods of fabricating the transistor cell. The transistor cell may include a substrate, an active region and a gate having a gate contact in the active region. The transistor cell may further include a first portion of a spacer of the gate contact formed from a first material, and a second portion of the spacer of the gate contact formed from a second material.

A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source / drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source / drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source / drain region present on a substrate; at least one fin disposed on the at least one bottom source / drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source / drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.

The present disclosure generally relates to semiconductor processing for self-aligned gate structures and corresponding semiconductor devices. In an example, a semiconductor device includes a semiconductor substrate (102), a semiconductor gate layer (110), an offset dielectric layer (112), and a gate metal contact (114). The semiconductor gate layer (110) is over the semiconductor substrate (102). The offset dielectric layer (112) is over the semiconductor gate layer (110). The gate metal contact (114) is over the offset dielectric layer (112) and passes through an opening through the offset dielectric layer (112). The gate metal contact (114) contacts the semiconductor gate layer (110) through the opening through the offset dielectric layer (112). A first sidewall (140) of the semiconductor gate layer (110), a second sidewall (142) of the offset dielectric layer (112), and a third sidewall (144) of the gate metal contact (114) are vertically aligned over the semiconductor substrate (102).

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Semiconductor devices with self-aligned gate isolation and wrap around source / drain contacts are provided. In one aspect, a semiconductor device includes: at least a first FET (FET1) and a second FET (FET2), adjacent to one another on a wafer; a dielectric bar between gates of the FET1 and the FET2, and between source / drain regions of the FET1 and the FET2; and wrap around source / drain contacts that at least partially surround the source / drain regions of the FET1 and the FET2. A shallow trench isolation (STI) region can be present between the FET1 and the FET2 and the dielectric bar can be centered over, and directly contact the STI region. Portions of the dielectric bar between the gates and between the source / drain regions can have a height H1 and H2, respectively, where H1>H2. A method of fabricating the present semiconductor device is also provided.

A self-aligned gate end cap (SAGE) architecture with an improved cap is described, as well as a method of manufacturing a self-aligned gate end cap (SAGE) architecture with an improved cap. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over the second semiconductor fin. A gate cap isolation structure is between the first gate structure and the second gate structure. The gate end cap isolation structure has a higher-k dielectric cap layer on the lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen, and has a monoclinic crystallinity of 70% or more.

A self-aligned gate end cap (SAGE) architecture with gate-all-around devices. A self-aligned gate end cap (SAGE) architecture with a gate-all-around device, and a method of manufacturing a self-aligned gate end cap (SAGE) architecture with a gate-all-around device, are described. In an example, an integrated circuit structure includes a semiconductor fin over a substrate and having a length in a first direction. The nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, the second direction being perpendicular to the first direction. A semiconductor device includes a pair of gate end cap isolation structures, where a first one of the pair of gate end cap isolation structures is equidistantly spaced from a first side of a semiconductor fin while a second one of the pair of gate end cap isolation structures is spaced from a second side of the semiconductor fin.

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Embodiments of this disclosure relate to a split-gate channel MOS transistor having a self-aligned gate region and a body region. A method for fabricating an integrated device having at least one MOS transistor integrated on a die of semiconductor material is proposed. The method includes forming one or more gate trenches having corresponding field plates and gate regions. The body region is formed by selectively implanting dopant along one or more implantation directions inclined relative to the front surface of the die. Furthermore, corresponding integrated devices and systems including such integrated devices are proposed.

The invention relates to a semiconductor device with a self-aligned gate and a field plate and a manufacturing method thereof. An embodiment of a semiconductor device includes a semiconductor substrate and one or more lower dielectric layers on a surface of the substrate. Source, drain, gate and field plate openings formed in a self-aligned manner extend through the lower dielectric layer to the substrate. A conformal dielectric layer is disposed over the lower dielectric layer and into the gate and field plate openings. The conformal dielectric layer includes a first portion on a sidewall of the gate opening, a second portion on a sidewall of the field plate opening, and a third portion on the substrate at a bottom range region of the field plate opening. A gate spacer is formed on the first portion of the conformal dielectric layer. A gate electrode in the gate opening contacts the gate spacer and the semiconductor substrate. A field plate in the field plate opening contacts the second and third portions of the conformal dielectric layer.

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source / drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source / drain features disposed over a substrate. The channel layer extends along a first direction between the source / drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source / drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source / drain features disposed over a substrate. The channel layer extends along a first direction between the source / drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Self-aligned gate isolation / cutting techniques for multigate devices are disclosed herein. An exemplary multigate device includes a first gate having a gate stack that surrounds a semiconductor layer. The first gate is disposed between a first gate isolation wall and a second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, and the first sidewall is formed by the gate dielectric and the gate electrode. A gate endcap is disposed on the first sidewall. A gate helmet is disposed over the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate helmet. A gate contact is disposed on the first gate. The gate contact extends over the first gate isolation wall and connects the first gate to a second gate.

Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

A microelectronic structure that includes a first nanosheet transistor that includes a first source / drain and a second nanosheet transistor that includes a second source / drain. A first frontside source / drain contact that includes a horizontal section and a protrusion section. The horizontal section of the first frontside source / drain contact is in contact with the flat horizontal frontside surface of the first source / drain. The protrusion section of the first frontside source / drain contact is in contact with the at least one inclined side surface of the first source / drain. A second frontside source / drain contact that includes a horizontal section and at least one protrusion section. The horizontal section of the second frontside source / drain contact is in contact with the flat horizontal frontside surface of the second source / drain. The at least one protrusion section of the second frontside source / drain contact is in contact with the at least one inclined side surface of the second source / drain.

The invention relates to a self-aligned gate cut with a hybrid architecture. Techniques are provided herein for forming a semiconductor device that includes one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure surrounding or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors having a gate cut-out extending through at least an entire thickness of the gate structure and including a dielectric material. The gate cut-out includes a hybrid design formed in two portions. A first portion of the gate cut-out is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second portion of the gate cut-out is formed over the first portion of the gate cut-out and integrated with a spacer structure formed on sidewalls of the sacrificial gate extending over adjacent fins.

A semiconductor device is provided that includes a self-aligned gate cut structure electrically isolating, at least in part, a gate structure of a first transistor from a gate structure of a second transistor. The distance from a semiconductor channel region of the first transistor to the self-aligned gate cut structure is the same as the distance from a semiconductor channel region of the second transistor to the self-aligned gate cut structure.

Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.