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37results about How to "Increase deposition thickness" patented technology

Device and method for realizing three-dimensional printing micro-nano structure by utilizing alternating-current electrospining

InactiveCN106182785AIncreasing the thicknessAvoid changes in the electric field distributionAdditive manufacturing apparatusThree dimensional modelNanofiber
The invention provides a device and a method for realizing a three-dimensional printing micro-nano structure by utilizing alternating-current electrospining. The method comprises the following steps of: putting printing raw materials into an injecting system, and forming spherical liquid drops of the printing raw materials at a needle head; applying alternating-current high-voltage electricity to the needle head and a receiving plate, and forming alternating high-voltage electric fields between the needle head and the receiving plate, enabling the printing raw materials to form single jet flow under the action of the alternating high-voltage electric fields, and depositing the single jet flow on the receiving plate to form micro-nano fibers; enabling the temperature of the receiving plate to be stabilized to be lower than a smelting point of the printing raw materials, and curing micro-nano fibers; controlling the receiving plate to move, thereby obtaining layered sections of a three-dimensional model; and sequentially scanning each layer of the three-dimensional model to complete printing of the three-dimensional model. The method can effectively improve three-dimensional printing precision.
Owner:NORTHWESTERN POLYTECHNICAL UNIV

Zero-mode waveguide hole wall modification method and zero-mode waveguide hole structure

The invention provides a zero-mode waveguide hole wall modification method. The method comprises the following steps: covering a polymer; irradiating ultraviolet light on the surface of a metal covering layer to form a first chemical bond; and stripping the polymer. The invention also relates to a zero-mode waveguide hole structure. The hole wall of the zero-mode waveguide hole is covered with thepolymer, and ultraviolet light irradiates the surface of the metal covering layer for bonding to form a high-refractive-index non-reflective first chemical bond; the in-hole volume of the zero-mode waveguide hole can be reduced by increasing the deposition thickness of the first chemical bond of the high-refractive-index non-reflective material, so that free nucleotides in the hole can be significantly reduced, and the signal-to-noise ratio can be improved. Besides, the position of excited fluorescence can be far away from the metal wall of the zero-mode waveguide hole by depositing the firstchemical bond of a high-refractive-index non-reflective material in the hole, so that the fluorescence cannot be weakened or even quenched, and the detection is more sensitive while the fluorescenceeffect is enhanced.
Owner:SUZHOU INST OF BIOMEDICAL ENG & TECH CHINESE ACADEMY OF SCI

Array substrate and preparation method thereof

The invention relates to the technical field of display, especially to an array substrate and a preparation method thereof. The array substrate and the preparation method thereof are used to solve theproblem that overlap regions between a gate and a source and a drain are prone to short circuit in the related art, which causes the decrease of panel yield. The embodiments of the invention providesthe array substrate. Multiple TFTs are arranged on the array substrate. Each TFT includes an active layer, a gate insulating layer, a gate, a first interlayer insulating layer, a second interlayer insulating layer, a source and a drain which are arranged on the substrate in order. Each source and drain are in contact with the corresponding active layer at least passing through a hole through thecorresponding first interlayer insulating layer. Each second interlayer insulating layer includes a first insulation pattern. Each first insulation pattern is located between the corresponding first interlayer insulating layer and the corresponding source and the corresponding drain and is located in the area where the corresponding TFT is located. Each first insulation pattern at least covers anoverlap region between the corresponding source and the corresponding drain and the side surface of the corresponding gate in the area where the corresponding TFT is located. The array substrate and the preparation method thereof are used for production and manufacturing of display panels.
Owner:HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD +1

Manufacturing method for deep trough isolation structure

The invention provides a manufacturing method for a deep trough isolation structure. The manufacturing method is characterized in that a semiconductor substrate is provided, a shallow trough isolationstructure and a grid are formed in the semiconductor substrate; a first dielectric layer is formed, the first dielectric layer covers the semiconductor substrate, the shallow trough isolation structure and the grid, and thickness of the first dielectric layer is greater than thickness of a target side; an opening is formed, the opening penetrates through the first dielectric layer and the shallowtrough isolation structure, and the semiconductor substrate is exposed; the first dielectric layer is taken as a mask, and the semiconductor substrate is etched in the opening to form a deep trough;the first dielectric layer on the surface of the semiconductor substrate, the surface of the shallow trough isolation structure and a top surface of the grid is removed, the first dielectric layer ona side wall of the grid is reserved to form a side wall structure, and thickness of the side wall structure is thickness of the target side wall; a second dielectric layer is formed, and the deep trough is filled by the second dielectric layer to form the deep trough isolation structure.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

A kind of array substrate and preparation method thereof

The present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof. The method is used to solve the problem in the related art that the overlapping area between the gate, the source and the drain is prone to short circuit, which causes the yield rate of the panel to decrease. An embodiment of the present invention provides an array substrate, on which a plurality of TFTs are arranged, and each TFT includes an active layer, a gate insulating layer, a gate, a first interlayer insulating layer, The second interlayer insulating layer, the source electrode and the drain electrode; the source electrode and the drain electrode are in contact with the active layer at least through the via holes penetrating the first interlayer insulating layer; the second interlayer insulating layer includes a first insulating pattern, the first The insulating pattern is located between the first interlayer insulating layer and the source and drain, and is located in the area where the TFT is located. The first insulating pattern at least covers the overlapping area of ​​the side of the source, the drain and the gate in the area where the TFT is located. The embodiments of the present invention are used in the production and manufacture of display panels.
Owner:HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD +1
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