322 results about "Tunnel effect" patented technology

Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.

Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si / Ge TFETs resulting in ultra-high on-chip transistor densities.

In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV / decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.

Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these elongate monocrystalline nanostructure Si / Ge TFETs resulting in ultra-high on-chip transistor densities.

Tunneling-effect converters of thermal energy to electricity with an emitter and a collector separated from each other by a distance that is comparable to atomic dimensions and where tunneling effect plays an important role in the charge movement from the emitter to the collector across the gap separating such emitter and collector. At least one of the emitter and collector structures includes a flexible structure. Tunneling-effect converters include devices that convert thermal energy to electrical energy and devices that provide refrigeration when electric power is supplied to such devices.

Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

The present invention is one kind of environment friendly composite emulsified asphalt material for grouting and repairing cracks in highway and building. The composite emulsified asphalt material consists of emulsified asphalt40-90 weight portions, powdered inorganic material 50-90 weight portions, nanometer material 5-10 weight portions, polymer emulsion 20-40 weight portions and water 30-80 weight portions mainly. The composite emulsified asphalt material has nanometer particle component with unique surface effect, small size effect and tunnel effect, polymer emulsion component resulting in high interface combining force and high antiaging performance, and inorganic material powder component resulting in high wear resistance, high strength, etc., so that it has high comprehensive performance, good crack repairing effect and low cost.

Tunnel effect magnetoresistance comprising, in the form of a stack:a first layer (12) of free magnetisation magnetic material,a "barrier" layer (16), composed of an electrically insulating material, anda second layer (14) of trapped magnetisation magnetic material,According to the invention, the thickness of the first layer (12) of magnetic material is less than 10 nm.The invention may be particularly applied to the manufacture of magnetic data read heads.

The invention provides a high-speed detection system and method of tunnel defects. The system comprises a master control unit, a linear laser, an area array charge coupled device (CCD) camera, an image compression unit, a displacement sensor, a synchronous controller, an image storage unit, a storage module, a correction module and an inertial navigator. A special measurement locomotive serves as a mobile monitoring platform for the design and is particularly suitable for subway tunnel monitoring, and subway and other tunnel space structures can be effectively, rapidly and dynamically measured; the actually measured data is compared with actual real distance, errors are analyzed, the parameter setting is adjusted, and the measurement accuracy is greatly improved; moreover, the XYZ axial vibration of the mobile monitoring platform is subjected to error correction through the inertial navigator, and a measurement error is prevented from being introduced into mobile measurement.

The present invention relates to a light-emitting device having a substrate and a light-emitting layer comprising an electroluminescent material, wherein the light-emitting layer (p-n junction) is sandwiched between a p-type cladding layer with a p-electrode layer and an n-type cladding layer with an n-electrode layer. The light-emitting device is characterized in that a light control portion is deposited on a light-exiting surface of the light-emitting device. Said light control portion comprises at least one light-tunneling layer. Said light-tunneling layer has a refractive index with respect to the wavelength of the main emitting-light from the light-emitting layer lower than the refractive indices of the substrate, the cladding layers and the electrode layers. The light extraction efficiency is increased by the light tunneling effect when the emitting-light emitted by the light-emitting layer enters the interface between the epitaxial layer and the surrounding material with an incident angle larger than the critical angle. The tunneling light from the light control portion can be polarized, such that a polarized light-emitting device can be realized in practice.

A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

An electronics enclosure implementing a cooling system and method enables much higher power densities in air-cooled electronic enclosures. The system includes an air streaming or "tunneling effect" ventilation system, including an enclosure that functions as a heat transfer component of the system, that efficiently removes warm air from the interior of the enclosure. The ventilation system comprises an array of intake fans on a first side panel of the enclosure, an array of exhaust fans on an opposing side panel of the enclosure, and a substantially unobstructed channel between the side panels. Additionally, an external heat exchanger is provided that is integrated with the enclosure for dissipation of heat from high-density powered components such as hard drives. The system further includes a thermoelectric cooling module with a heat exchanger and an optional externally ported CPU fan to achieve superior heat dissipation from the CPU.

A modified emulsion asphalt compounded by inorganic nano-particles and polymer contains 200-700 parts by weight of asphalt, 2-80 parts by weight of modified inorganic nano-particles, 5-50 parts by weight of styrene-butadiene rubber latex, and 170-793 parts by weight of water, wherein the modified inorganic nano-particles is prepared by mixing 95-98 parts by weight of inorganic nano-particles with 2-5 parts by weight of coupling agent, and each components are mixed, followed by normal emulsion treatment to get the emulsion asphalt. The invention utilizes unique surface effect, small size effect and macroscopic quantum tunneling effect etc. of the inorganic nano-particles to give the product comprehensive properties, such as good wear resistance, intensity sum, anti-aging property and fine waterproof effect etc. Using the invention can increase the road maintenance cycle and decrease the cost. Furthermore, the water-proof cost of construction industry is greatly decreased.

Refractive index changing apparatus includes quantum dots each having discrete energy levels including ground level and excited level, the excited level being higher than the ground level even if energy due to ambient temperature is provided on the quantum dots, barrier structure unit formed of dielectric which surrounds the quantum dots, injection unit configured to inject an electron into position of the ground level in each quantum dot via the barrier structure unit, utilizing tunneling effect, or to prevent injection of an electron into the position, injecting the electron or preventing injection of the electron controlled by changing an energy level of the injection unit, source which emits, to the quantum dots, first light beam having first energy for exciting electrons from the ground level to the excited level, and source which emits, to the quantum dots, second light beam having second energy different from the first energy.

Structures and methods involving non volatile depletion mode p-channel memory cells with an ultrathin tunnel oxide thicknesses, e.g. less than 50 Angstrom (Å), have been provided. Write and erase operations are performed by tunneling. The floating gate of the depletion mode p-channel memory cell is adapted to hold a fixed charge over a limited range of floating gate potentials or electron energies. There is a range potentials applied to the floating gate for which there are no final nor initial states in the silicon substrate or p+ source region. In this range of potentials there can be no charge leakage from the floating gate by tunneling or thermally assisted tunneling. The charge state of the floating gate will modulate the conductivity of the underlying transistor channel, with different stable and non-volatile charge states resulting in different conductivity states. Other aspects are also included.

The invention discloses a carbonaceous schist tunnel blasting method and construction method. The carbonaceous schist tunnel construction method includes the steps of carrying out blasting in the carbonaceous schist tunnel blasting method, clearing away residues and digging out rock mass which does not fall off by using mechanical equipment, and revising a tunnel contour line. The carbonaceous schist tunnel blasting method includes the steps of dividing a tunnel face into a carbonaceous schist area and a none-carbonaceous schist area; arranging a plurality of blast holes in the tunnel face to form a hole pattern, wherein the density of the blast holes in the carbonaceous schist area is smaller than that of the blast holes in the none-carbonaceous schist area; filling explosives and detonators into the blast holes; connecting the detonators into a network; detonating the explosives according to a preset detonating sequence. The tunneling method of combining blasting and machinery is adopted, blasting is carried out first, rock does not need to be thrown out completely, and therefore disturbance and damage to surrounding rock are reduced; then the residues are cleared away and the rock mass which does not fall off is dug out by using the mechanical equipment, thus, tunneling efficiency can be improved, disturbance to the surrounding rock is little, and damage on the surrounding rock is reduced; in addition, the back break control effect is good, the tunneling effect is improved, and tunneling quality is high.

The invention discloses an ionic type memristor having a quantum conductance effect. The ionic type memristor has a "sandwich" structure or a field effect transistor structure. The ionic type memristor having the "sandwich" structure is composed of a top electrode, a tunneling layer, an oxide layer, an ion-doped layer and a bottom electrode. The specific structure is as follows: "the top electrode / the tunneling layer / the oxide layer / the ion-doped layer / the bottom electrode", "the top electrode / the oxide layer / the ion-doped layer / the tunneling layer / the bottom electrode" and "the top electrode / the oxide layer / the tunneling layer / the ion-doped layer / the bottom electrode". The top electrode has a thickness of 30-100 nm. The tunneling layer has a thickness of 0.34-5 nm. The oxide layer has a thickness of 10-40 nm. The ion-doped layer has a thickness of 10-40 nm. The bottom electrode has a thickness of 30-100 nm. The ionic type memristor of the invention can produce a memristive effect based on alkali metal or alkali metal ionic migration; and can achieve a quantum conductance effect using a tunneling effect when ions penetrate through the tunneling layer or a quantum size effect of a nanowire channel on the ions, so that multiple quantum states are observed.

There is provided a 3-terminal negative differential resistance field effect element having a high output and high frequency characteristic, requiring low power consumption, and preferably having a high PVCR. The field effect element uses a compound hetero structure and forms a dual channel layer by connecting a high-transfer degree quantum well layer (13) to a low-transfer degree quantum dot layer (15) via a barrier layer (14) on a substrate (11). Under existence of an electric field obtained by voltage application to a gate electrode (17), the negative resistance field effect element (10) changes a carrier accelerated by a drain voltage applied to a drain electrode (19) from a high-transfer degree channel to a low-transfer degree channel by the tunnel effect or over the barrier layer, thereby exhibiting negative differential resistance for the drain current and changing the negative resistance inclination by the gate voltage.

The present invention provides a magnetic sensor having a space-saving coil of low power consumption for generating a bias magnetic field applied to a magnetoresistive effect element. A magnetic sensor comprises a thin-film-like magnetic tunnel effect element (magnetoresistive effect element) 11. A coil 21 is disposed in a plane under the magnetic tunnel effect element 11 and parallel to a thin-planar film surface of the element. The coil 21 is a double spiral type coil which includes a first spiral conductor portion 21-1 and a second spiral conductor portion 21-2. The magnetic tunnel effect element 11 is disposed between a spiral center P1 of the first conductor portion 21-1 and a spiral center P2 of the second conductor portion 21-2 in a plan view. The first and second conductor portions 21-1 and 21-2 are connected such that electric currents in the same direction pass through a part of the first conductor portion 21-1 that overlaps the magnetic tunnel effect element 11 in a plan view and through a part of the second conductor portion 21-2 that overlaps the magnetic tunnel effect element 11 in a plan view.

A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV / decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.

A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer formed on a substrate, an active layer formed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed on the active layer, an undoped GaN layer formed on the p-type nitride semiconductor layer, an AlGaN layer formed on the undoped GaN layer to form a two-dimensional electron gas (2DEG) layer at a bonding interface between the AlGaN layer and the undoped GaN layer, and an n-side electrode and a p-side electrode respectively formed on the n-type nitride semiconductor layer and the AlGaN layer to be connected to each other. As a hetero-junction structure of GaN / AlGaN is formed on the p-type nitride semiconductor layer, contact resistance between the p-type nitride semiconductor layer and the p-side electrode is enhanced by virtue of tunneling effect through the 2DEG layer.

On a single chip are formed a plurality of magnetoresistance effect elements provided with pinned layers having fixed magnetization axes in the directions that cross each other. On a substrate 10 are formed magnetic layers that will become two magnetic tunnel effect elements 11, 21 as magnetoresistance effect elements. Magnetic-field-applying magnetic layers made of NiCo are formed to sandwich the magnetic layers in plan view. A magnetic field is applied to the magnetic-field-applying magnetic layers. The magnetic field is removed after the magnetic-field-applying magnetic layers are magnetized in the direction shown by arrow A. As a result of this, by the residual magnetization of the magnetic-field-applying magnetic layers, magnetic fields in the directions shown by arrows B are applied to the magnetic layers that will become magnetic tunnel effect elements 11, 21, whereby the magnetization of the pinned layers of the magnetic layers that will become magnetic tunnel effect elements 11, 21 is pinned in the directions shown by arrows B.

Apparatus and method for modifying an object with electrons are provided, by which the object can be uniformly and efficiently modified with the electrons under a pressure substantially equal to atmospheric pressure even when having a relatively wide surface area to be treated. This method uses a cold-cathode electron emitter having the capability of emitting electrons from a planar electron emitting portion according to tunnel effect, and preferably comprising a pair of electrodes, and a strong field drift layer including nanocrystalline silicon disposed between the electrodes. The object is exposed to electrons emitted from the planar electron emitting portion by applying a voltage between the electrodes. It is preferred that an energy of the emitted electrons is selected from a range of 1 eV to 50 keV, and preferably 1 eV to 100 eV.

Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

A nonvolatile memory has a problem in that applied voltage is high. This is because a carrier needs to be injected into a floating gate through an insulating film by a tunneling effect. In addition, there is concern about deterioration of the insulating film by performing such carrier injection. An object of the present invention is to provide a memory in which applied voltage is lowered and deterioration of an insulating film is prevented. One feature is to use a layer in which an inorganic compound having a charge-transfer complex is mixed with an organic compound as a layer functioning as a floating gate of a memory. A specific example is an element having a transistor structure where a layer in which an inorganic compound having a charge-transfer complex is mixed with an organic compound and which is sandwiched between insulating layers is used as a floating gate.

In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.