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98 results about "Substrate coupling" patented technology

In an integrated circuit, a signal can couple from one node to another via the substrate. This phenomenon is referred to as substrate coupling or substrate noise coupling. The push for reduced cost, more compact circuit boards, and added customer features has provided incentives for the inclusion of analog functions on primarily digital MOS integrated circuits (ICs) forming mixed-signal ICs. In these systems, the speed of digital circuits is constantly increasing, chips are becoming more densely packed, interconnect layers are added, and analog resolution is increased. In addition, recent increase in wireless applications and its growing market are introducing a new set of aggressive design goals for realizing mixed-signal systems. Here, the designer integrates radio frequency (RF) analog and base band digital circuitry on a single chip. The goal is to make single-chip radio frequency integrated circuits (RFICs) on silicon, where all the blocks are fabricated on the same chip. One of the advantages of this integration is low power dissipation for portability due to a reduction in the number of package pins and associated bond wire capacitance. Another reason that an integrated solution offers lower power consumption is that routing high-frequency signals off-chip often requires a 50Ω impedance match, which can result in higher power dissipation. Other advantages include improved high-frequency performance due to reduced package interconnect parasitics, higher system reliability, smaller package count, and higher integration of RF components with VLSI-compatible digital circuits. In fact, the single-chip transceiver is now a reality.

Modified Antenna Ground Plane For Space-Constrained Designs

Described herein are unmanned aerial vehicles (UAVs) and antenna assemblies thereof for shaping radiation patterns in global positioning system applications. For example, an embodiment pertains to an antenna assembly onboard an aerial vehicle. The antenna assembly includes a radiating element coupled to a chassis of an aerial vehicle and positioned in parallel with the chassis, a substrate coupled to the radiating element, a ground plane coupled to the substrate, and a feed cable coupled to the radiating element through the substrate and the ground plane. The ground plane includes a center portion in parallel with the chassis and with the radiating element, and side portions positioned at an angle relative to the chassis and to the radiating element.
Owner:SKYDIO INC

Micro-cooling systems and devices with associated methods of fabrication and use

This disclosure includes description of various micro-cooling devices, systems, and methods. An example micro-cooling device includes a first substrate, a second substrate coupled to the first substrate, and a microfluidic channel formed between the first substrate and the second substrate. The example micro-cooling device further includes a fluid contained within the microfluidic channel, and a set of one or more piezoelectric actuators positioned adjacent to the microfluidic channel and configured to govern flow of the fluid within the microfluidic channel. An example micro-cooling system includes one or more of the micro-cooling devices as well as one or more sensors and control circuitry coupled to the one or more sensors and configured to govern operation of the micro-cooling device(s) accordingly.
Owner:TDK USA CORP

Package comprising an embedded heat pipe

A device comprising a board; a first package coupled to the board through a plurality of solder interconnects, wherein the first package comprises: a first substrate; a first integrated device coupled to the first substrate; a heat pipe coupled to the first integrated device through a thermal interface material; a second package coupled to the first substrate through a through a plurality of inter substrate interconnects; and an encapsulation layer located between the first substrate and the second package.
Owner:QUALCOMM INC

Integrated circuit package device with a power delivery substrate

A integrated circuit (IC) package device includes a first substrate, an IC device mounted to a first surface of the first substrate, a second substrate, and first power delivery circuitry. The second substrate is mounted to a second surface of the first substrate. The first surface is opposite the second surface. The second substrate includes a decoupling capacitor. The first power delivery circuitry is mounted to the second substrate and coupled to the IC device through the second substrate and the first substrate.
Owner:ADVANCED MICRO DEVICES INC

Rfsoi wafer with low substrate leakage and manufacturing method therefor

The present invention relates to the technical field of semiconductors, and in particular to an RFSOI wafer with low substrate leakage and a manufacturing method therefor. The RFSOI wafer comprises, successively arranged from top to bottom, a first silicon layer, a first buried oxide layer, a first defect-rich layer, a second buried oxide layer, a second defect-rich layer and a wafer substrate, each of the first defect-rich layer and the second defect-rich layer being any one of a polycrystalline silicon layer and a porous silicon layer. In the present invention, providing the second defect-rich layer can effectively block the interference of a substrate layer with electric signals in a back gate region, and providing the second buried oxide layer can block the leakage of the original TRL / SUB layer. Therefore, compared with existing RFSOI wafers, the RFSOI wafer of the present invention has lower back gate leakage and a capability of isolating the substrate coupling effect.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD

Package substrate for a semiconductor device

This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.
Owner:MICRON TECHNOLOGY INC

Substrate Coupling System and Method

A wiring harness installation assembly includes a first member and a second member. The first member includes a locking tab. The second member includes an upper surface and a side surface. The side surface extends from the upper surface. The upper surface and the side surface define an aperture. The aperture includes a first portion and a second portion. The first portion is formed in the side surface. The second portion is formed in the upper surface. The first portion is configured to receive the locking tab. The second portion is configured to receive a tool operable to engage the locking tab.
Owner:APTIV MANUFACTURING MANAGEMENT SERVICES GMBH

Electronic devices and methods of manufacturing electronic devices

In one example, an electronic device includes a first substrate and a second substrate. The first substrate includes a substrate first side, a substrate second side, and a first conductive structure. An inner electronic component is coupled to the first conductive structure proximate to the substrate second side. An outer electronic component is coupled to the first conductive structure proximate to the substrate first side. The outer electronic component includes a body and a groove in the body configured to couple with an external interconnect. Inner interconnects couple the first substrate to the second substrate. The first substrate, the second substrate, the inner electronic component, and the outer electronic component are in a stacked configuration. The inner electronic component is interposed between the first substrate and the second substrate. Other examples and related methods are also disclosed herein.
Owner:AMKOR TECH SINGAPORE HLDG PTE LTD

Laser heat sinking for integrating laser diode into recording heads at wafer level

PendingUS20260024957A1Reducing temperature influence on carrierArm with optical waveguideWaveguideMaterials science
A method comprising the steps of forming a recording head comprising a waveguide, a heat sink and a bleed resistor on a first substrate, is described. The bleed resistor is coupled to the heat sink and the substrate. The top surface of the heat sink is planarized to form a planarized heat sink. A laser diode formed on a second substrate is transfer printed onto the planarized heat sink to form an integrated laser diode.
Owner:SEAGATE TECH LLC

System and method of manufacturing semiconductor device

PendingKR1020260139645ADevice materialLaser assisted
The system of the present disclosure comprises a laser assisted bonding (LAB) tool including: a stage block having a top side, a bottom side, and a lateral side extending between the top side and the bottom side; a first vertical laser source positioned above the top side of the stage block and facing the top side of the stage block; and a second vertical laser source positioned below the bottom side of the stage block and facing the bottom side of the stage block, wherein: the top side of the stage block is configured to support a substrate and a first electronic component including a first interconnect coupled to the substrate; and the first vertical laser source is configured to emit a first vertical laser beam at a first vertical angle with respect to the top side of the substrate toward a substrate positioned on the top side of the stage block in order to induce a first heat in the first interconnect to bond the first interconnect to the substrate. The second vertical laser source is configured to emit a second vertical laser beam vertically at a second vertical angle relative to the bottom surface of the substrate toward the bottom surface of the stage block to induce a second row in the first interconnect; the first row and the second row can bond the first interconnect to the substrate.
Owner:AMKOR TECH SINGAPORE HLDG PTE LTD

Impingement cooling in high power package

PendingUS20260206592A1Coolant flowElectronic component
This application is directed to cooling a semiconductor system. The semiconductor system includes a device substrate having a first surface and a second surface, an electronic component thermally coupled to the device substrate, and a cooling substrate coupled to the device substrate. The cooling substrate includes a third surface facing the second surface of the device substrate, a fourth surface opposite the third surface, and a plurality of vias between the third and fourth surfaces. The second surface and the third surface define a cavity therebetween, such that in use coolant flows from the fourth surface through the plurality of vias to exit at the third surface, enters the cavity between the second and third surfaces, and impinges on the second surface. At least a portion of one or more of the device substrate and the cooling substrate have similar coefficients of thermal expansion.
Owner:CAES SYSTEMS LLC

Switch with back gate-connected compensation capacitors

A disclosed structure (e.g., a switch circuit) includes multiple transistors (e.g., on triple wells) connected in series between a first and second nodes. Each transistor can include a primary gate (e.g., a front gate) for controlling the ON / OFF state of the transistor and a secondary gate (e.g., a back gate) for adjusting the VT of the transistor. The switch circuit further includes multiple capacitors (e.g., APMOM capacitors on triple wells), each connected to the second node and to the secondary gate of a corresponding one of the transistors. In advanced semiconductor-on-insulator processing technology platforms, each secondary gate includes a well region within a semiconductor substrate and a corresponding section of an insulator layer, which is on the semiconductor substrate and adjacent to an active device region for the transistor. The capacitors are preselected during design and different capacitances for limiting parasitic secondary gate-to-substrate coupling. Also disclosed are associated methods.
Owner:GLOBALFOUNDRIES US INC

Heat dissipation structure in advanced chip package

A device including: a substrate; a chip module coupled to the substrate; a first thermal material disposed on the chip module; a second thermal material disposed on the chip module; a lid structure disposed over the chip module and coupled to the substrate with adhesive along a perimeter of the lid structure, wherein a central portion of the lid structure is in thermal contact with the first thermal material and the second thermal material; and a support structure arranged around the chip module and covered by the lid structure, the support structure extending vertically from the substrate to the lid structure.
Owner:INTEL CORP

Circuit systems

Various circuit board systems and methods of use and manufacture thereof are disclosed. A circuit board system can have a first circuit board including a substrate and a first component susceptible to electromagnetic interference carried by the substrate. The system can also include a second circuit board including a second substrate, and a shield engaged to the substrate of the first component, the shield at least partially covering the first component and being configured to protect the first component from electromagnetic interference, wherein the shield couples the substrate of the first circuit board to the substrate of the second circuit board.
Owner:SNAP INC

Head Unit And Liquid Ejecting Apparatus

A head unit includes: a head having a piezoelectric element which is displaced in response to application of a drive signal, and including an ejecting section which ejects ink in response to the displacement of the piezoelectric element; a heater that heats the ink; a temperature abnormality detection section that detects a temperature abnormality and outputs an abnormality detection signal; a heater stop section that stops an operation of the heater in response to the abnormality detection signal; and a head substrate coupled to the head, in which the heater stop section is mounted in an analog manner on the head substrate.
Owner:SEIKO EPSON CORP

Lid for optical packages

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including an optical package or co-packaged optics package comprising a lid. In an embodiment, an optical package can include a first substrate, a first circuit coupled to the first substrate and configured to transmit or receive an electrical signal, a second circuit coupled to the first substrate and configured to transmit or receive an optical signal, and a lid configured to couple to the first substrate and configured to cover at least a portion of the first circuit or the second circuit.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

Package with a substrate comprising embedded escape interconnects and surface escape interconnects

A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.
Owner:QUALCOMM INC

PERFORMANCE MODULE WITH RELIABILITY CHARACTERISTICS

A device can include a substrate. A device can include a metal portion of the package that is coupled to the substrate, the metal portion being configured to act as an electrical connection to the semiconductor die. A device can include a die region on the substrate. A device can include a barrier that surrounds at least a portion of the die region. A device can include a flexible material that is positioned between the die region and the barrier. A device can include an encapsulation material that surrounds the substrate and the metal portion of the package.
Owner:SEMICON COMPONENTS IND LLC

Synchronizer for electrocautery

A synchronizer for electrocautery includes a grip and an electrode unit coupled with the grip. The grip includes a first inner substrate; a second inner substrate coupled and aligned with the first inner substrate to form an internal channel; a circuit board coupled with the first inner substrate; a pivot disposed on the first inner substrate; and a lever unit. The internal channel has a first opening; a second opening in opposite to the first opening; and the third opening between the first opening and the second opening. A lever unit has a proximal end, disposed on the first inner substrate and coupled with the pivot; a distal end, aligned with the third opening; a first protruding point located between the proximal end and the distal end and aligned with the coagulation switch. The electrode includes an electrode partially disposed within the internal channel, and coupled with the circuit board.
Owner:VIGEON TECHNOLOGY CO LTD +1

Vivaldi antenna structures with concurrent transmit and receive

Provided herein are various enhancements for antenna systems and directed radio frequency energy structures. In one example, an apparatus includes an antenna array comprising a plurality of Vivaldi antenna elements arranged about an axis perpendicular to a baseplate. Feed elements are coupled to each of the Vivaldi antenna elements through the baseplate. First alternating ones of the Vivaldi antenna elements are configured to transmit radio frequency (RF) energy at a first RF band, and second alternating ones of the Vivaldi antenna elements are configured to receive RF energy at a second RF band.
Owner:LOCKHEED MARTIN CORP

Electronic devices with sidewall antennas and methods of fabricating such devices

An electronic device includes a device substrate with a mounting surface, an electronic circuit coupled to the mounting surface, and encapsulant material over the electronic circuit and the mounting surface. The encapsulant material has an upper encapsulant surface and a plurality of encapsulant sidewalls extending between the mounting surface of the device substrate and the upper encapsulant surface. The electronic device also includes a sidewall antenna coupled to one of the encapsulant sidewalls, and a shield structure embedded within the encapsulant material between the sidewall antenna and the electronic circuit. The sidewall antenna is electrically coupled to the electronic circuit through the device substrate. The shield structure extends from the mounting surface of the device substrate toward the upper surface of the encapsulant material. The sidewall antenna may be selected from an end-fire type of antenna and a broadside-fire type of antenna.
Owner:NXP USA INC

Acoustic transducer with improved low-frequency response

ActiveUS12673864B2Cantilevered beamTransducer
Aspects of acoustic transducers are described. One aspect is a microelectromechanical (MEMS) transducer comprising a substrate and multiple cantilevered beams. A first cantilevered beam comprises a first protrusion and a first piezoelectric structure, where the first piezoelectric structure comprises a first deflection end and a first fixed end, where the first fixed end is coupled to the substrate, and where the first deflection end is cantilevered away from the substrate. The first cantilevered beam is separated from a second cantilevered beam by a gap. The first protrusion is disposed at the first deflection end and increases a thickness of the first cantilevered beam along the gap at the first deflection end. A second protrusion of the second beam is disposed at a second deflection end and increases a thickness of the second cantilevered beam along the gap at the second deflection end.
Owner:QUALCOMM INC

Temperature sensing assembly and battery module including the same

A temperature sensing assembly according to an embodiment of the disclosure may include a substrate; a temperature sensor mounted at the substrate; and a bridge coupled to the substrate and at which a hole facing the temperature sensor is defined. A compression member is disposed between the bridge and the substrate, and is disposed at both sides of the temperature sensor.
Owner:LG ENERGY SOLUTION LTD

Package comprising an integrated device, a substrate and a heat sink

A package comprising a first substrate; an integrated device coupled to the substrate; a second substrate coupled to the first substrate through at least a plurality of solder interconnects, wherein the second substrate is located over a portion of the integrated device; and a heat sink coupled to a back side of the integrated device through a thermal interface material, wherein the heat sink is located over another portion of the integrated device, wherein the heat sink is located laterally to the second substrate.
Owner:QUALCOMM INC

Package comprising a substrate with post interconnects and a solder resist layer having a cavity

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.
Owner:QUALCOMM INC