226 results about "Nanocrystalline silicon" patented technology

A thin film silicon solar cell for use in photovoltaic cells having a carrier substrate, a front transparent conductive oxide contact, a thin film silicon solar cell layer having at least one layer of hydrogenated microcrystalline silicon or nanocrystalline silicon, and a back contact having a transparent conductive oxide contact layer and a back reflective layer comprising a white pigmented dielectric reflective media.

The invention discloses iron-based nanocrystalline soft-magnetic alloy with excellent high-frequency performance and a preparation method thereof. The expression of the alloy is FeaSibPcCuxMy, wherein a, b, c, x and y respectively represent the atomic percent content of corresponding compositions and satisfy the following conditions: 70<=a<=85, 5<=b<=15, 5<=c<=18, 0.0001<=x<=3, 0<=y<=5, a+b+c+x+y=100%, and M is one or more of Zr, Ti, Ta, Hf, Nb, V, W, Mo, Mn, Cr, Re, Zn, In, As, Sb, Bi, Ca, platinum group elements, rare earth elements, N, Sn, Ge, Ga and Al. The alloy is a nanocrystalline soft-magnetic alloy band prepared by employing a single-roller quick-cooling method under the conditions of high vacuum and argon protection. The alloy does not contain B elements, is good in soft magnetic property, high in thermal stability, low in high-frequency loss and low in magnetostriction coefficient.

The present invention describes nanocomposite material structures including layers forming p-n and p-i-n homo- and heterojunctions for application in photovoltaics, solar cells, photodetectors, and light emitting devices, comprising semiconductor nanoparticles, such as colloidal semiconductor nanocrystals, nanorods, nanowires, nanotubes, etc., wherein at least one of the layers is made of hydrogenated amorphous or microcrystalline/nanocrystalline silicon or their alloys enabling low-temperature fabrication processes preventing any degradation of physical properties of the nanoparticles.

A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.

One aspect of the present invention relates to a photovoltaic cell. In one embodiment, the photovoltaic cell includes a first conductive layer, an N-doped semiconductor layer formed on the first conductive layer, a first silicon layer formed on the N-doped semiconductor layer, a nanocrystalline silicon (nc-Si) layer formed on a first silicon layer, a second silicon layer formed on the nc-Si layer, a P-doped semiconductor layer on the second silicon layer, and a second conductive layer formed on the P-doped semiconductor layer, where one of the first silicon layer and the second silicon layer is formed of amorphous silicon, and the other of the first silicon layer and the second silicon layer formed of polycrystalline silicon.

The disclosed methods and apparatus concern Raman spectroscopy using metal coated nanocrystalline porous silicon substrates. Porous silicon substrates may be formed by anodic etching in dilute hydrofluoric acid. A thin coating of a Raman active metal, such as gold or silver, may be coated onto the porous silicon by cathodic electromigration or any known technique. In certain alternatives, the metal coated porous silicon substrate comprises a plasma-oxidized, dip and decomposed porous silicon substrate. The metal-coated substrate provides an extensive, metal rich environment for SERS, SERRS, hyper-Raman and/or CARS Raman spectroscopy. In certain alternatives, metal nanoparticles may be added to the metal-coated substrate to further enhance the Raman signals. Raman spectroscopy may be used to detect, identify and/or quantify a wide variety of analytes, using the disclosed methods and apparatus. In some disclosed methods, Raman spectroscopy may be used to detect nucleotides, purines or pyrimidines at the single molecule level.

A lower electrode (2) and surface electrode (7) composed of a layer-structured conductive carbide layer is formed on one principal surface side of the substrate (1) composed of an insulative substrate such as a glass or ceramic substrate. A non-doped polycrystalline silicon layer (3) is formed on the lower electrode (2), An electron transit layer (6) composed of an oxidized porous polycrystalline silicon is formed on the polycrystalline silicon layer (3). The electron transit layer (6) is composed of a composite nanocrystal layer including polycrystalline silicon and many nanocrystalline silicons residing adjacent to a grain boundary of the polycrystalline silicon. When voltage is applied between the lower electrode (2) and the surface electrode (7) such that the surface electrode (7) has a higher potential, electrons are injected from the lower electrode (2) toward the surface electrode (7), and emitted through the surface electrode (7) through the electron transit layer (6).

A thin film transistor (TFT) and the method of forming the same is provided. The method of forming the TFT on a surface of a substrate, includes the steps of: forming a gate electrode; deposing a gate dielectric on the gate electrode; forming a nanocrystalline silicon (nc-Si) layer and an amorphous silicon (a-Si:H) layer above the gate dielectric, so that the thickness of the nc-Si layer is less than 30 nm thereby reducing off-current; and forming a source/drain electrode. The TFT includes: a gate electrode on a substrate, a gate dielectric on the gate electrode; a nc-Si layer having a thickness less than 30 nm, thereby reducing off-current; an a-Si:H layer; and a source/drain electrode.

A multilayer coating (MLC) is composed of two chemically different layered nanocrystalline materials, nanodiamond (nanoD) and nano-cubic boron nitride (nono-cBN). The structure of the MLC and fabrication sequence of layered structure are disclosed. The base layer is preferably nanoD and is the first deposited layer serving as an accommodation layer on a pretreated substrate. It can be designed with a larger thickness whereas subsequent alternate nano-cBN and nanoD layers are typically prepared with a thickness of 2 to 100 nm. The thickness of these layers can be engineered for a specific use. The deposition of the nanoD layer, by either cold or thermal plasma CVD, is preceded by diamond nucleation on a pretreated and/or precoated substrate, which has the capacity to accommodate the MLC and provides excellent adhesion. Nano-cBN layers are directly grown on nanodiamond crystallites using ion-assisted physical vapor deposition (PVD) and ion-assisted plasma enhanced chemical vapor deposition (PECVD), again followed by nanodiamond deposition using CVD methods in cycles until the intended number of layers of the MLC is obtained.

The invention relates to a lamination solar battery. The lamination solar battery is composed of an amorphous silicon film top battery, a perovskite middle battery and a nanocrystalline silicon bottom battery, or has a double-lamination structure taking an amorphous silicon film battery as a top battery and a perovskite battery as a bottom battery. The optical band gaps of three materials, i.e., amorphous silicon, perovskite and nanocrystalline silicon (crystalline silica) match well (1.75eV, 1.5eV and 1.12eV) so that light of different wavebands can be absorbed segment by segment. The amorphous silicon film top battery and the nanocrystalline silicon bottom battery (or the crystalline silica, nanocrystalline silicon germanium and amorphous silicon germanium) clamp the perovskite therebetween so as to protect the perovskite battery and reduce the influence exerted by atmosphere and water on the perovskite battery. At the same time, the amorphous silicon top battery can absorb ultraviolet light so as to protect a perovskite sub-battery. Besides, an amorphous silicon layer at the top has better UV and blue light response than the perovskite battery so that the defects of the perovskite middle battery are made up for.

A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 100 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

Disclosed is an electron source 10 including an electron source element 10a formed on the side of one surface of an insulative substrate 1. The electron source element 10a includes a lower electrode 2, a composite nanocrystal layer 6 and a surface electrode 7. The composite nanocrystal layer 6 includes a plurality of polycrystalline silicon grains 51, a thin silicon oxide film 52 formed over the surface of each of the grains 51, a number of nanocrystalline silicons 63 residing between the adjacent grains 51, and a silicon oxide film 64 formed over the surface of each of the nanocrystalline silicons 63. The silicon oxide film 64 is an insulating film having a thickness less than the crystal grain size of the nanocrystalline silicon 63. The surface electrode 7 is formed of a carbon thin film 7a laminated on the composite nanocrystal layer 6 while being in contact therewith, and a metal thin film 7b laminated on the carbon thin film 7a.

A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II-VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.

Apparatus and method for modifying an object with electrons are provided, by which the object can be uniformly and efficiently modified with the electrons under a pressure substantially equal to atmospheric pressure even when having a relatively wide surface area to be treated. This method uses a cold-cathode electron emitter having the capability of emitting electrons from a planar electron emitting portion according to tunnel effect, and preferably comprising a pair of electrodes, and a strong field drift layer including nanocrystalline silicon disposed between the electrodes. The object is exposed to electrons emitted from the planar electron emitting portion by applying a voltage between the electrodes. It is preferred that an energy of the emitted electrons is selected from a range of 1 eV to 50 keV, and preferably 1 eV to 100 eV.

A solar call is provided along with a method for forming a semiconductor nanocrystalline silicon insulating thin-film with a tunable bandgap. The method provides a substrate and introduces a silicon (Si) source gas with at least one of the following source gases: germanium (Ge), oxygen, nitrogen, or carbon into a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. A SiOxNyCz thin-film embedded with a nanocrystalline semiconductor material is deposited overlying the substrate, where x, y, z≧0, and the semiconductor material is Si, Ge, or a combination of Si and Ge. As a result, a bandgap is formed in the SiOxNyCz thin-film, in the range of about 1.9 to 3.0 electron volts (eV). Typically, the semiconductor nanoparticles have a size in a range of 1 to 20 nm.

Open circuit voltage of a photovoltaic device including a p-i-n junction including amorphous silicon-containing semiconductor materials is increased by a high power plasma treatment on an amorphous p-doped silicon-containing semiconductor layer before depositing an amorphous intrinsic silicon-containing semiconductor layer. The high power plasma treatment deposits a thin layer of nanocrystalline silicon-containing semiconductor material or converts a surface layer of the amorphous p-doped silicon containing layer into a thin nanocrystalline silicon-containing semiconductor layer. After deposition of an intrinsic amorphous silicon layer, the thin nanocrystalline silicon-containing semiconductor layer functions as an interfacial nanocrystalline silicon-containing semiconductor layer located at a p-i junction. The increase in the open circuit voltage of the photovoltaic device through the plasma treatment depends on the composition of the interfacial crystalline silicon-containing semiconductor layer, and particularly on the atomic concentration of carbon in the interfacial crystalline silicon-containing semiconductor layer.

A forming method and a forming apparatus of nanocrystalline silicon structure makes it possible to prepare a nanocrystalline silicon structure at a low temperature to have densely packed silicon crystal grains which are stably terminated and to effectively control the grain size in nanometer scale. A forming method and a forming apparatus of nanocrystalline silicon structure with oxide or nitride termination, carry out a first step of treating a surface of a substrate with hydrogen radical; a second step of depositing silicon crystals having a grain size of 10 nm or less by the thermal reaction of a silicon-containing gas; and a third step of terminating the surface of the silicon crystal with oxygen or nitrogen by using one of oxygen gas, oxygen radical and nitrogen radical.

A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).

The invention discloses a heat treatment method for preparing nanocrystalline alloy. According to the method, during the nanocrystalline alloy material preparation by an amorphous crystallization method, a heat treatment process is divided into two steps; in the first step, the characteristics of high heat conductivity and low heat capacity of an amorphous crystallization alloy belt material are used; the fast temperature rise and short-time heat insulation pre-heating treatment is performed; high-density and uniformly-distributed crystal nucleuses are formed in the belt material through excitation; then, in the second step of conventional nano-crystallization heat treatment, high-density crystal particles grow synchronously; the competitive effect between the crystal particles is used for promoting the crystal particle refining. Compared with the existing heat treatment method, the method has the advantages that amorphous crystallization nucleation and crystal particle growth processes are controlled in a separated way; the crystal particle density and the crystallization degree are improved; the crystal particle dimension and the distribution uniformity are improved; in addition, the crystal particles are refined, so that the performance of the alloy is improved.