459 results about "Intrinsic semiconductor" patented technology

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked. An impurity serving as an electron donor (donor) which is contained in the stacked body of an oxide semiconductor is removed in a step of crystal growth; therefore, the stacked body of an oxide semiconductor is highly purified and is an intrinsic semiconductor or a substantially intrinsic semiconductor whose carrier density is low. The stacked body of an oxide semiconductor has a wider band gap than a silicon semiconductor.

In a stacked-layer type photoelectric conversion device, a plurality of photoelectric conversion units are stacked on a substrate, each of which includes a one conductivity-type layer, a photoelectric conversion layer of substantially intrinsic semiconductor and an opposite conductivity-type layer in this order from a light-incident side. At least one of the opposite conductivity-type layer in a front photoelectric conversion unit arranged relatively closer to the light-incident side and the one conductivity-type layer in a back photoelectric conversion unit arranged adjacent to the front photoelectric conversion unit includes a silicon composite layer at least in a part thereof. The silicon composite layer has a thickness of more than 20 nm and less than 130 nm and an oxygen concentration of more than 25 atomic % and less than 60 atomic %, and includes silicon-rich phase parts in an amorphous alloy phase of silicon and oxygen.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

The present invention provides a photodiode comprising a p-i-n or pn junction at least partly formed by first and second regions (2) made of semiconductor materials having opposite conductivity type, wherein the p-i-n or pn junction comprises a light absorption region (11) for generation of charge carriers from absorbed light. One section of the p-i-n or pn junction is comprises by one or more nanowires (7) that are spaced apart and arranged to collect charge carriers generated in the light absorption region (11). At least one low doped region (10) made of a low doped or intrinsic semiconductor material provided between the nanowires (7) and one of said first region (1) and said second region (2) enables custom made light absorption region and/or avalanche multiplication region of the active region (9).

A photodiode may include a first region comprising substantially intrinsic semiconductor material, the region having a first side and a second side opposite to the first side. The photodiode may also include a second region comprising highly-doped p-type semiconductor material formed proximate to the first side of the first region. The photodiode may additionally include a third region comprising highly-doped n-type semiconductor material formed proximate to the second side of the first region. The photodiode may further include a fourth region comprising one of: (i) highly-doped p-type semiconductor formed between the first region and the third region, or (ii) highly-doped n-type semiconductor formed between the first region and the second region.

A method for forming a thin film photovoltaic device. The method provides a transparent substrate including a surface region. A first electrode layer overlies the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. At least the multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a bulk copper indium disulfide. The bulk copper indium disulfide material has a surface region characterized by a copper poor surface region having a copper to indium atomic ratio of less than about 0.95:1 and n-type impurity characteristics. The bulk copper indium disulfide material excluding the copper poor surface region forms an absorber region and the copper poor surface region forms at least a portion of a window region for the thin film photovoltaic device. The method optionally forms a high resistivity transparent material having an intrinsic semiconductor characteristic overlying the copper poor surface region. A second electrode layer overlies the high resistivity transparent layer.

Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 micrometer, preferably greater than 3 micrometer, more preferably greater than or equal to 10 micrometer.

Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that can serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 μm, preferably greater than 3 μm, more preferably greater than or equal to 10 μm, and end portions of one of electrodes that are in contact with the oxide semiconductor is placed inside end portions of the oxide semiconductor.

A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon.

A solar cell includes a semiconductor substrate, a first intrinsic semiconductor layer and a second intrinsic semiconductor layer on the semiconductor substrate, the first intrinsic semiconductor layer and the second intrinsic semiconductor layer being spaced apart from each other, a first conductive semiconductor layer and a second conductive semiconductor layer respectively disposed on the first intrinsic semiconductor layer and the second intrinsic semiconductor layer, and a first electrode and a second electrode, each including a bottom layer on the first conductive semiconductor layer and the second conductive semiconductor layer, respectively, the bottom layer including a transparent conductive oxide, and an intermediate layer on the bottom layer, the intermediate layer being including copper.

A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

A photovoltaic device having multiple photoelectric conversion cells disposed in a tandem configuration and a chemical vapor deposition method for fabricating the same are disclosed. Each photoelectric conversion cell has a different band gap energy and includes a p-type semiconductor layer, an intrinsic semiconductor layer and an n-type semiconductor layer in sequential touching contact. Each semiconductor layer is formed of a nano-crystalline semiconductor containing silicon as a principal constituent. The semiconductor layer may be deposited by a novel chemical vapor deposition method which utilizes plasma and laser energies simultaneously to decompose a film forming gas, thereby forming a semiconductor film on a substrate. The chemical vapor deposition process may be carried out on a continuously conveying substrate, thereby permitting high throughput production of the photovoltaic device.

This invention provides an innovative multi-line structure and an effective four-terminal method for the resistivity measurement of semiconductor materials. The multi-line structure and the four-terminal method not only allow one to perform resistivity measurement on any inorganic and organic semiconductor thin film conveniently, rapidly and accurately but also offer the means to study resistivity uniformity across the semiconductor thin film.

The invention provides an LED flip chip manufacturing method and an LED flip chip. The method includes the steps of sequentially growing a buffer layer, an intrinsic semiconductor layer, an N type semiconductor layer, a light-emitting layer and a P type semiconductor layer on a substrate so as to form an epitaxial layer, removing part of the P type semiconductor layer and part of the light-emitting layer to expose part of the N type semiconductor layer, sequentially forming a transparent conducting layer and a DBR layer on the surface of the P type semiconductor layer, forming a metal reflection layer on the surface of the DBR layer, forming through holes in the same positions of the DBR layer and the metal reflection layer to expose part of the N type semiconductor layer and part of the transparent conducting layer, and forming metal conducting layers on the through holes of the DBR layer and the through holes of the metal reflection layer. By means of the method, the problems that when the LED flip chip is manufactured based on the existing technology, due to the limitation of the performance of metal materials, the requirement for the reflection rate and the requirement for electrical conductivity can not be taken into consideration at the same time when the metal reflection layer is manufactured, and the reflection efficiency is lowered are solved.