137 results about "Intrinsic semiconductor" patented technology

A back-contact battery and a manufacturing method therefor, which relate to the technical field of photovoltaics, and are used for reducing the number of defects on a second surface side and improving the photoelectric conversion efficiency of the back-contact battery. The back-contact battery comprises: a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer and a second doped semiconductor layer. The first doped semiconductor layer comprises a first doped part and a second doped part, wherein the first doped part is located on a first region, and the second doped part is located on an isolation region; and the doping concentration of impurities in the second doped part is lower than that of impurities in the first doped part. The intrinsic semiconductor layer is formed on the part of the isolation region outside the second doped part in a direction parallel to a second surface. The second doped semiconductor layer covers a second region, the electrical conduction type of the second doped semiconductor layer is opposite to the electrical conduction type of the first doped semiconductor layer, and the intrinsic semiconductor layer is used for electrically isolating the first doped semiconductor layer from the second doped semiconductor layer.

The invention discloses a back contact cell and a manufacturing method thereof, relates to the technical field of photovoltaics, and aims to prevent electric leakage between doped semiconductor layers with opposite conduction types in the back contact cell. The back contact cell includes a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer, and an insulating mask layer. The part, located on the first region, of the first doped semiconductor layer is a first doped part, and the other part is a second doped part. The doping concentration of impurities in the second doping part is smaller than that of the impurities in the first doping part. The intrinsic semiconductor layer is formed on a portion of the isolation region outside the second doped portion, and is integrally formed with the first doped semiconductor layer. And the second doped semiconductor layer covers the second region, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conduction types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer and a P-type semiconductor layer. The P-type semiconductor layer comprises a Si3N4 layer, a first superlattice layer and a second superlattice layer which are sequentially stacked on the electron blocking layer, the first superlattice layer comprises a Mg-doped Al < x > Ga < 1-x > N layer and a Mg-doped GaN layer which are alternately stacked, and the second superlattice layer comprises a non-doped GaN layer and a Mg-doped In < y > Ga < 1-y > N layer which are alternately stacked. By implementing the invention, the luminous efficiency of the light-emitting diode can be improved.

The invention relates to an optical switch and an optical communication network switching chip. The optical switch comprises a substrate, a first insulating layer and a phase shift layer which are stacked in sequence, the phase shift layer comprises a first positive doped region, a first multimode interference device and a first negative doped region, the first multimode interference device is a ridge waveguide, and at least part of the ridge waveguide is an intrinsic semiconductor; the first positive doped region and the first negative doped region are located on the two sides of the ridge-shaped waveguide, and the first positive doped region, the ridge-shaped waveguide and the first negative doped region form a first PIN phase shifter which is used for switching the on-off state of the optical switch; the ridge waveguide comprises a first input waveguide, a second input waveguide, a first output waveguide and a second output waveguide, the first input waveguide and the second input waveguide are located on the first side of the ridge waveguide, the first output waveguide and the second output waveguide are located on the second side of the ridge waveguide, and the first input waveguide is opposite to the first output waveguide; the second input waveguide is opposite to the second output waveguide. The switching speed of the optical switch can be improved, and optical loss can be reduced.

The invention discloses a self-aligned double-epitaxial super-junction MOSFET and a manufacturing method, the self-aligned double-epitaxial super-junction MOSFET comprises a semiconductor layer arranged on a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; and the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are oppositely arranged; the semiconductor substrate is provided with first regions and second regions which are alternately arranged along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate; the first semiconductor layer is arranged on the first surface and located in the first region; the first semiconductor layer comprises an intrinsic semiconductor part and a doped semiconductor part, and the orthographic projection of the intrinsic semiconductor part on the semiconductor substrate is located between the orthographic projection of the doped semiconductor part on the semiconductor substrate and the second region; the first electrode is arranged on the first surface and is in ohmic contact with the doped semiconductor part of the first semiconductor layer; the second electrode is arranged on the first surface and is in ohmic contact with the semiconductor substrate; the first electrode and the second electrode are opposite in polarity. Electric leakage of the solar cell can be improved.

The invention provides a display panel, a display device and a preparation method of a PIN diode, and relates to the technical field of semiconductors. Since the array layer of the display panel forms a plurality of film layers by adopting an ion implantation mode in the preparation process, the PIN diode is integrated in the array layer firstly, and then the P-type semiconductor layer is prepared by adopting the ion implantation mode used in the preparation process of the array layer in the preparation process of the array layer, so that the P-type semiconductor layer can be prepared in the preparation process of the array layer. The purposes of simplifying the preparation process flow and reducing the production cost are achieved. Furthermore, the ion implantation depth of the first doped ions is smaller than the thickness of the P-type semiconductor layer, and a diffusion space is provided for diffusion of the first doped ions in the region of the P-type semiconductor layer in which the first doped ions are not directly implanted, so that the depth of the first doped ions diffused to the intrinsic semiconductor layer is reduced to the greatest extent, and the diffusion efficiency of the intrinsic semiconductor layer is improved. And the photoelectric property of the PIN diode is ensured.

The present application relates to a solar cell, a method for manufacturing the same, a photovoltaic module, and a photovoltaic system. The solar cell includes: an intrinsic semiconductor substrate including an intrinsic region, a first surface, and a second surface, the first surface and the second surface being disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region being disposed between the first surface and the second surface; a first doping structure having a first doping type, the first doping structure being disposed on a side of the intrinsic region close to the first surface; a second doping structure having a second doping type, the second doping structure being disposed on a side of the intrinsic region close to the second surface; wherein the first doping type and the second doping type are opposite to each other, and the first doping structure, the intrinsic region, and the second doping structure form a p-i-n structure. On the one hand, the present application can reduce the complexity and manufacturing cost of the solar cell manufacturing process, and on the other hand, can improve the conversion efficiency of the solar cell.

A process for the synthesis of a multilayer gamma-graphdiyne, which is a sp2 / sp1 allotrope of carbon having intrinsic semiconductor properties, by crystallization-assisted irreversible cross-coupling polymerization.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

The invention relates to a back contact solar cell, a manufacturing method thereof and a photovoltaic module. The manufacturing method of the back contact solar cell comprises the steps of providing a substrate; correspondingly forming a first intrinsic semiconductor layer and a second intrinsic semiconductor layer on the first surface and the second surface of the substrate; forming a first doping layer and a second doping layer which are arranged at an interval and are opposite in doping type on one side, deviating from the substrate, of the second intrinsic semiconductor layer, and forming a first passivation layer laid on one sides, deviating from the substrate, of the first doping layer and the second doping layer, enabling the first passivation layer to expose a first metal region of the first doping layer and a second metal region of the second doping layer; obtaining a solar cell main body; the first intrinsic semiconductor layer of the solar cell main body faces upwards and is connected with an electroplating cathode; enabling the first metal region and the second metal region of the solar cell main body to face downwards and to be in contact with electroplating liquid with an electroplating anode; and correspondingly forming a first electrode and a second electrode in the first metal region and the second metal region of the solar cell main body.

A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

The invention relates to a solar cell and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a front surface and a back surface which are oppositely arranged; the back surface is a polished surface; the first intrinsic semiconductor layer is arranged on the back surface; the first doped microcrystalline silicon layer is arranged on one side, far away from the semiconductor substrate, of the first intrinsic semiconductor layer; the first doped microcrystalline silicon layer comprises a plurality of first microcrystal grains; wherein the ratio of the length of the first microcrystal grains to the thickness of the first doped microcrystal silicon layer is a, and a meets the following relational expression: a is more than or equal to 0.8 and less than or equal to 1.1; the included angle between the length direction of the first microcrystal grains and the thickness direction of the first doped microcrystal silicon layer is alpha, and alpha meets the following relational expression that alpha is larger than or equal to 0 degree and smaller than or equal to 45 degrees. The battery efficiency can be improved, and the preparation cost can be reduced.

A preparation method of a passivated contact structure includes: forming a tunneling layer on a semiconductor substrate; forming an intrinsic semiconductor layer on the tunneling layer; forming a doped layer containing a dopant on the intrinsic semiconductor layer, and performing an activation treatment on the doped layer to diffuse the dopant in the doped layer into the intrinsic semiconductor layer to form a doped semiconductor layer. The tunneling layer and the doped semiconductor layer form the passivated contact structure.

This application discloses a photodetector, its fabrication method, and a display panel. The fabrication method includes the following steps: forming an N-type semiconductor layer; forming an intrinsic semiconductor layer on the N-type semiconductor layer; placing the N-type semiconductor layer and the intrinsic semiconductor layer into a vacuum chamber, and introducing BF3, B2H6, and SiH4 into the vacuum chamber to form a P-type semiconductor layer doped with boron ions, fluorine ions, and hydrogen ions on the intrinsic semiconductor layer, thereby completing the fabrication of the photodetector. Through the above design, the embodiments of this application can improve the detection sensitivity of the photodetector to low-energy X-rays, medium-energy X-rays, and high-energy X-rays, and improve the detection performance of the photodetector in different scenarios.

The present disclosure provides semiconductor devices and photonic circuits. The semiconductor device includes a substrate and an optical modulator disposed on the substrate. The optical modulator includes a first electrical coupling portion having a first type doping, a second electrical coupling portion having a second type doping, and an optical coupling portion disposed between the first electrical coupling portion and the second electrical coupling portion, where the optical coupling portion includes an intrinsic semiconductor. The optical modulator is configured to receive a first voltage through the first electrical coupling portion and the second electrical coupling portion to decrease a resonant wavelength of the optical modulator.

The invention discloses a self-aligned double-epitaxial super-junction IGBT and a manufacturing method, the self-aligned double-epitaxial super-junction IGBT comprises a semiconductor layer arranged on the front surface of a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls; the collector region layer and the buffer region layer are sequentially arranged below the surface of the back surface of the substrate. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, the drift region can be changed into the intrinsic semiconductor layer, and the on-resistance is reduced while the withstand voltage is improved.

To provide a semiconductor device in which transistors with different characteristics, specifically a transistor with the excellent dynamic characteristic (on characteristic or frequency characteristic (called f-characteristic)) and a transistor with suppressed off current are provided on the same substrate, and provide a method for manufacturing the semiconductor device by a simple method.SOLUTION: An oxide semiconductor layer that is intrinsic or substantially intrinsic and includes a crystal region on a surface is used for a transistor. As the semiconductor that is intrinsic or substantially intrinsic, a semiconductor from which impurities to become electron donors in the oxide semiconductor are removed and which has a larger energy gap than the silicon semiconductor is used. By controlling the potential of a pair of conductive films disposed above and below the oxide semiconductor layer through an insulating film so as to change the position of a channel to be formed in the oxide semiconductor layer, the electric characteristic of the transistor may be controlled.SELECTED DRAWING: Figure 1

The embodiment of the invention discloses a light-emitting chip and a preparation method thereof, and the method comprises the steps: arranging a stripping function layer which is made of the same material as an intrinsic semiconductor layer corresponding to a first semiconductor layer at the bottom of an isolation channel of adjacent light-emitting units; in this way, the materials of the contact interfaces of the light-emitting units and the substrate and the materials of the isolation channels between the adjacent light-emitting units and the contact interfaces of the substrate are close, so that when the substrate is stripped, the connection between the stripping function layer and the light-emitting units on the two sides is tighter; the overall structure of the light-emitting units and the stripping function layer on the substrate can be stripped from the substrate conveniently, the structural integrity of the obtained light-emitting chip is ensured, breakage at the position of an isolation channel of the adjacent light-emitting units is avoided, and the yield and reliability of the light-emitting chip are improved.

There is provided a radio frequency, RF, device (100, 102, 104, 106) comprising: an active semiconductor layer (110) comprising a front surface (112) and a rear surface (114); and an RF transmission line (120) coupled to the front surface (112) of the active semiconductor layer (110), the RF transmission line (120) comprising an active region (121), the active region (121) causing the RF transmission line (120) to comprise a first state in which the RF transmission line (120) has a first radio frequency transmission property, and a second state in which the RF transmission line (120) has a second radio frequency transmission property, wherein the RF transmission line (120) is selectively switchable between the first state and the second state in response to illuminati on of the active semiconductor layer (110) by a light source (210) when in use, and wherein the active semiconductor layer (110) comprises an intrinsic semiconductor material with a thickness, between the front surface (112) and the rear surface (114), of less than 100 microns.

The present invention relates to the technical field of light emitting diodes. Disclosed are a flip-chip LED array and a manufacturing method therefor. The manufacturing method comprises the following steps: (1) fixing one side of a substrate of each flip-chip LED to an adhesive film layer, so as to obtain a chip array; (2) soldering pads of the chip array to solder joints of a packaging substrate; and stripping off the adhesive film layer to obtain a soldered array; (3) removing the substrates and intrinsic semiconductor layers of the flip-chip LEDs of the soldered array, so as to obtain a first intermediate array; (4) forming a reflection layer between adjacent flip-chip LEDs of the first intermediate array, so as to obtain a second intermediate array; and (5) forming a fluorescent layer on the side of the second intermediate array away from the packaging substrate, so as to obtain a finished flip-chip LED array. Implementing the present invention can improve the brightness, the yield and the reliability and prolong the service life of flip-chip LED arrays, and further can shorten the manufacturing process and reduce the product cost.

The present application relates to a solar cell and a preparation method therefor, a photovoltaic module and a photovoltaic system. The solar cell (1) comprises: an intrinsic semiconductor substrate (111), comprising an intrinsic region (111a), a first surface (111b) and a second surface (111c), the first surface (111b) and the second surface (111c) being provided on two opposite sides of the intrinsic semiconductor substrate (111), and the intrinsic region (111a) being provided between the first surface (111b) and the second surface (111c); a first doping structure (112) having a first doping type, the first doping structure (112) being provided on the side of the intrinsic region (111a) close to the first surface (111b); and a second doping structure (113) having a second doping type, the second doping structure (113) being provided on the side of the intrinsic region (111a) close to the second surface (111c), wherein the first doping type is opposite to the second doping type, and the first doping structure (112), the intrinsic region (111a) and the second doping structure (113) form a p-i-n structure.

The invention discloses a back contact cell and a manufacturing method thereof, relates to the field of photovoltaic technology, and is used for reducing the number of defects on one side of a second surface and improving the photoelectric conversion efficiency of the back contact cell. The back contact battery comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer and a second doped semiconductor layer. The first doped semiconductor layer comprises a first doped part and a second doped part, the first doped part is partially located on the first region, and the second doped part is partially located in the isolation region; and the doping concentration of impurities in the second doping part is smaller than that of impurities in the first doping part. And the intrinsic semiconductor layer is formed on the part, except the second doping part, of the isolation region in the direction parallel to the second surface. The second doped semiconductor layer covers the second region, the conduction type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer, and the intrinsic semiconductor layer is used for electrically isolating the first doped semiconductor layer from the second doped semiconductor layer.

A heterojunction cell and a method for preparing same. The heterojunction cell comprises: a semiconductor substrate layer; and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on the surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises: a bottom intrinsic layer; and a wide-band-gap intrinsic layer, which is located on the surface of the side of the bottom intrinsic layer that is away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer being greater than the band gap of the bottom intrinsic layer. The band gap of a wide-band-gap intrinsic layer is larger, and when sunlight irradiates a heterojunction cell, photons, the energy of which is less than that of the band gap of the wide-band-gap intrinsic layer, cannot be subjected to parasitic absorption.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

The application discloses a back contact cell and a manufacturing method thereof, and relates to the technical field of photovoltaics, which is used for preventing leakage between doped semiconductor layers with opposite conductive types in the back contact cell. The back contact cell comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer and an insulating mask layer. The first doped semiconductor layer is divided into a first doped part and a second doped part. The second doped part is smaller than the first doped part in impurity doping concentration. The intrinsic semiconductor layer is formed on the part of the second doped part of the isolation area and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second area, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conductive types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

This invention discloses a nuclear battery based on a three-dimensional through-hole structure and its fabrication method. The nuclear battery includes a three-dimensional through-hole PIN junction semiconductor transducer unit, a radiation source, and an electrode layer. The unit, from top to bottom, consists of a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer. The radiation source is filled in the intrinsic semiconductor through-holes, while the P-type and N-type semiconductor through-holes are filled with electrically insulating materials. The method includes: obtaining a PIN structure on a semiconductor substrate; etching a three-dimensional through-hole array; fabricating a metal seed layer at the bottom of the array; filling the N-type semiconductor through-holes with conductive materials; filling the intrinsic semiconductor through-holes with radiation source material; filling the P-type semiconductor through-holes with electrically insulating materials; and converting the conductive materials in the N-type semiconductor through-holes into electrically insulating materials. This invention improves the energy deposition of radioactive decay particles within the intrinsic layer and the conversion efficiency of radioactive decay energy to electrical energy, thus achieving the fabrication of a high-output performance nuclear battery.

In order to overcome the problems that the existing wide band gap semiconductor material has a large number of spontaneous defects, it is difficult to obtain intrinsic semiconductor and it is difficult to realize reverse type doping, the application discloses a method which can controllably improve the formation energy of spontaneous defects and simultaneously reduce the formation energy of reverse type doping defects by applying voltage, realizes the preparation of intrinsic wide band gap semiconductor material and reverse type doping. The method comprises the following operation steps: during the growth of intrinsic wide band gap semiconductor material and reverse type doping process, a positive bias is applied to the wide band gap semiconductor material which spontaneously forms N type conduction, and a negative bias is applied to the wide band gap semiconductor material which spontaneously forms P type conduction. The application also discloses the application of the above method in the preparation of intrinsic zinc oxide and P type doped zinc oxide.

The embodiment of the present invention provides a photoelectric conversion structure, a manufacturing method thereof, an image sensor and an electronic device, including an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer, wherein the intrinsic semiconductor layer includes an amorphous silicon layer and a polycrystalline silicon layer arranged in layers. The present invention arranges the intrinsic semiconductor layer into a composite structure in which an amorphous silicon layer and a polycrystalline silicon layer are arranged in layers, so that the absorption advantages of the amorphous silicon layer and the polycrystalline silicon layer for light of different wavelengths can be combined, and the light absorption efficiency of the intrinsic semiconductor layer can be effectively improved, so that the intrinsic semiconductor layer can achieve a higher photoelectric conversion capability, thereby improving the external quantum efficiency and sensitivity of the photoelectric conversion structure.