13 results about "Intrinsic semiconductor" patented technology

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

The invention relates to a solar cell and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a front surface and a back surface which are oppositely arranged; the back surface is a polished surface; the first intrinsic semiconductor layer is arranged on the back surface; the first doped microcrystalline silicon layer is arranged on one side, far away from the semiconductor substrate, of the first intrinsic semiconductor layer; the first doped microcrystalline silicon layer comprises a plurality of first microcrystal grains; wherein the ratio of the length of the first microcrystal grains to the thickness of the first doped microcrystal silicon layer is a, and a meets the following relational expression: a is more than or equal to 0.8 and less than or equal to 1.1; the included angle between the length direction of the first microcrystal grains and the thickness direction of the first doped microcrystal silicon layer is alpha, and alpha meets the following relational expression that alpha is larger than or equal to 0 degree and smaller than or equal to 45 degrees. The battery efficiency can be improved, and the preparation cost can be reduced.

A preparation method of a passivated contact structure includes: forming a tunneling layer on a semiconductor substrate; forming an intrinsic semiconductor layer on the tunneling layer; forming a doped layer containing a dopant on the intrinsic semiconductor layer, and performing an activation treatment on the doped layer to diffuse the dopant in the doped layer into the intrinsic semiconductor layer to form a doped semiconductor layer. The tunneling layer and the doped semiconductor layer form the passivated contact structure.

This application discloses a photodetector, its fabrication method, and a display panel. The fabrication method includes the following steps: forming an N-type semiconductor layer; forming an intrinsic semiconductor layer on the N-type semiconductor layer; placing the N-type semiconductor layer and the intrinsic semiconductor layer into a vacuum chamber, and introducing BF3, B2H6, and SiH4 into the vacuum chamber to form a P-type semiconductor layer doped with boron ions, fluorine ions, and hydrogen ions on the intrinsic semiconductor layer, thereby completing the fabrication of the photodetector. Through the above design, the embodiments of this application can improve the detection sensitivity of the photodetector to low-energy X-rays, medium-energy X-rays, and high-energy X-rays, and improve the detection performance of the photodetector in different scenarios.

The application discloses a preparation method of intrinsic semiconductor carbon nanotube material. By using degradable conjugated polymer to replace commonly used separation polymer, separation and purification of semiconductor carbon nanotube and removal of surface polymer can be realized. The polymer used in the application can be quickly degraded under weak acid condition on the basis of ensuring the separation yield and high purity of the semiconductor carbon nanotube, and is decomposed into small molecules, so that the semiconductor carbon nanotube can show its intrinsic performance. Therefore, the semiconductor carbon nanotube material with intrinsic performance can be prepared by using the method of the application, the process is simple, the condition is mild, and the method is stable, efficient and can be widely applied to the carbon-based electronic field.

This application relates to a tandem solar cell, its fabrication method, and a photovoltaic module. The tandem solar cell includes a first cell structure and a second cell structure stacked together. The first cell structure includes: a semiconductor substrate having a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface; a tunneling layer and a first doped semiconductor layer stacked on the first surface and the first side surface; an intrinsic semiconductor layer and a second doped semiconductor layer stacked on the second surface and the first side surface; the surface of the semiconductor substrate has an overlapping region, the overlapping region being at least located on the first side surface, and a portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer stacked in the overlapping region along a direction away from the semiconductor substrate. Therefore, the tandem solar cell, its fabrication method, and the photovoltaic module provided in this application can improve the passivation effect of the tandem solar cell.

This invention discloses a photoelectrically tunable and dynamically switchable waveplate based on semiconductor metamaterials. Addressing the shortcomings of existing single-field modulation or simple superposition of multiple fields in doped semiconductors, such as high loss and poor coordination, this invention proposes a deep photoelectric-electrical synergistic modulation mechanism based on intrinsic semiconductors. The waveplate includes a substrate and a periodic array of intrinsic semiconductor cuboids formed thereon, with electrode structures at both ends. During modulation, a pump light is used as a pre-excitation condition to excite free carriers in the initially high-resistivity intrinsic semiconductor; simultaneously, a modulation voltage is applied to drive the nonlinear reconstruction of the spatial distribution and concentration of photogenerated carriers. Through the interlocking mechanism of the photoelectric dual fields, the effective dielectric constant and optical anisotropy of the cuboid units in the orthogonal directions are dynamically adjusted, thereby achieving efficient switching between multiple-dimensional polarization states, such as linear and circular polarization. This invention avoids the ohmic loss introduced by doping and has the advantages of compact structure, rich modulation dimensions, and high precision, making it suitable for fields such as optical communication and polarization imaging.

This application provides a semiconductor device and its fabrication method, as well as an electronic device, relating to the field of semiconductor technology, capable of reducing the subthreshold swing of transistors. The semiconductor device includes a transistor. The transistor includes a channel, a source, and a drain; the source and drain are disposed at opposite ends of the channel; a first intercalation layer is disposed between the source and the channel, and the first intercalation layer is in contact with both the source and the channel. The channel is made of a lightly doped semiconductor or an intrinsic semiconductor. The drain is made of a heavily doped semiconductor. The source is made of a P-type heavily doped semiconductor; wherein, the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor; or, the source is made of an N-type heavily doped semiconductor; the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor.

The disclosure provides bipolar transistor structures with a semiconductor base film within an opening of an isolation layer, and related methods. A structure according to the disclosure includes a semiconductor base film on a collector terminal. The semiconductor base film includes a first portion within an opening of an isolation layer. The first portion includes an intrinsic semiconductor. A second portion of the semiconductor base film is on the first portion. The second portion includes a sidewall adjacent the isolation layer and a lower surface on the isolation layer. A semiconductor film is on an upper surface of the first portion of the isolation layer and adjacent a sidewall of the second portion of the isolation layer. An emitter is on the semiconductor film.

Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source / drain regions are merged) or a PIN junction (e.g., first and second source / drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

This disclosure provides a radio frequency (RF) switch and electronic device, belonging to the field of RF technology, which at least partially solves the problems of large parasitic capacitance and low isolation in existing RF switches. The RF switch of this disclosure includes a substrate, and a semiconductor layer, a first interlayer insulating layer, and a connection electrode layer sequentially stacked on the substrate; the semiconductor layer includes a plurality of alternately arranged N-type semiconductors and a plurality of P-type semiconductors, and an intrinsic semiconductor sandwiched between the N-type and P-type semiconductors; the connection electrode layer includes a first connection electrode and a second connection electrode; the first connection electrode includes a plurality of first branches; the second connection electrode includes a plurality of second branches; the orthographic projections of an N-type semiconductor and a first branch on the substrate at least partially overlap, and the orthographic projections of a P-type semiconductor and a second branch on the substrate at least partially overlap; wherein at least some of the first branches extend in different directions.

A diode type ferroelectric tunnel junction memory comprises a substrate, a barrier regulation layer, an insulating medium layer, a ferroelectric material layer and a top electrode layer arranged in sequence, and the ferroelectric material layer provides polarization charges; the barrier regulation layer is made of intrinsic semiconductor material or doped semiconductor material opposite to the doping type of the substrate, and is located between the substrate and the ferroelectric layer to realize the adjustment of the barrier height. The application can increase the shielding length difference of the electrodes on both sides of the ferroelectric layer material of the memory by inserting an additional semiconductor barrier regulation layer on the basis of the traditional ferroelectric tunnel junction, so as to obtain an increased tunneling barrier width ratio and a storage window in the switching state. At the same time, the additional semiconductor barrier regulation layer and the substrate form a PN junction, so that the ferroelectric tunnel junction has obvious rectification characteristics and can be used for non-von neural morphological chip technology.

Comprehensive structure: a photodetector (14) in a semiconductor substrate (12); and a semiconductor material (24) on the photodetector (14), wherein the semiconductor material (24) comprises a semiconductor material of a first dopant type contacting an upper surface of the photodetector (14), a semiconductor material of a second dopant type contacting the upper surface of the photodetector (14), and intrinsic semiconductor material (24c) contacting the upper surface of the photodetector (14) and separating the semiconductor material of the first dopant type from the semiconductor material of the second dopant type.