67 results about "Intrinsic semiconductor" patented technology

The invention provides a display panel, a display device and a preparation method of a PIN diode, and relates to the technical field of semiconductors. Since the array layer of the display panel forms a plurality of film layers by adopting an ion implantation mode in the preparation process, the PIN diode is integrated in the array layer firstly, and then the P-type semiconductor layer is prepared by adopting the ion implantation mode used in the preparation process of the array layer in the preparation process of the array layer, so that the P-type semiconductor layer can be prepared in the preparation process of the array layer. The purposes of simplifying the preparation process flow and reducing the production cost are achieved. Furthermore, the ion implantation depth of the first doped ions is smaller than the thickness of the P-type semiconductor layer, and a diffusion space is provided for diffusion of the first doped ions in the region of the P-type semiconductor layer in which the first doped ions are not directly implanted, so that the depth of the first doped ions diffused to the intrinsic semiconductor layer is reduced to the greatest extent, and the diffusion efficiency of the intrinsic semiconductor layer is improved. And the photoelectric property of the PIN diode is ensured.

The present application relates to a solar cell, a method for manufacturing the same, a photovoltaic module, and a photovoltaic system. The solar cell includes: an intrinsic semiconductor substrate including an intrinsic region, a first surface, and a second surface, the first surface and the second surface being disposed on opposite sides of the intrinsic semiconductor substrate, and the intrinsic region being disposed between the first surface and the second surface; a first doping structure having a first doping type, the first doping structure being disposed on a side of the intrinsic region close to the first surface; a second doping structure having a second doping type, the second doping structure being disposed on a side of the intrinsic region close to the second surface; wherein the first doping type and the second doping type are opposite to each other, and the first doping structure, the intrinsic region, and the second doping structure form a p-i-n structure. On the one hand, the present application can reduce the complexity and manufacturing cost of the solar cell manufacturing process, and on the other hand, can improve the conversion efficiency of the solar cell.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

The invention relates to a solar cell and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a front surface and a back surface which are oppositely arranged; the back surface is a polished surface; the first intrinsic semiconductor layer is arranged on the back surface; the first doped microcrystalline silicon layer is arranged on one side, far away from the semiconductor substrate, of the first intrinsic semiconductor layer; the first doped microcrystalline silicon layer comprises a plurality of first microcrystal grains; wherein the ratio of the length of the first microcrystal grains to the thickness of the first doped microcrystal silicon layer is a, and a meets the following relational expression: a is more than or equal to 0.8 and less than or equal to 1.1; the included angle between the length direction of the first microcrystal grains and the thickness direction of the first doped microcrystal silicon layer is alpha, and alpha meets the following relational expression that alpha is larger than or equal to 0 degree and smaller than or equal to 45 degrees. The battery efficiency can be improved, and the preparation cost can be reduced.

A preparation method of a passivated contact structure includes: forming a tunneling layer on a semiconductor substrate; forming an intrinsic semiconductor layer on the tunneling layer; forming a doped layer containing a dopant on the intrinsic semiconductor layer, and performing an activation treatment on the doped layer to diffuse the dopant in the doped layer into the intrinsic semiconductor layer to form a doped semiconductor layer. The tunneling layer and the doped semiconductor layer form the passivated contact structure.

This application discloses a photodetector, its fabrication method, and a display panel. The fabrication method includes the following steps: forming an N-type semiconductor layer; forming an intrinsic semiconductor layer on the N-type semiconductor layer; placing the N-type semiconductor layer and the intrinsic semiconductor layer into a vacuum chamber, and introducing BF3, B2H6, and SiH4 into the vacuum chamber to form a P-type semiconductor layer doped with boron ions, fluorine ions, and hydrogen ions on the intrinsic semiconductor layer, thereby completing the fabrication of the photodetector. Through the above design, the embodiments of this application can improve the detection sensitivity of the photodetector to low-energy X-rays, medium-energy X-rays, and high-energy X-rays, and improve the detection performance of the photodetector in different scenarios.

The embodiment of the invention discloses a light-emitting chip and a preparation method thereof, and the method comprises the steps: arranging a stripping function layer which is made of the same material as an intrinsic semiconductor layer corresponding to a first semiconductor layer at the bottom of an isolation channel of adjacent light-emitting units; in this way, the materials of the contact interfaces of the light-emitting units and the substrate and the materials of the isolation channels between the adjacent light-emitting units and the contact interfaces of the substrate are close, so that when the substrate is stripped, the connection between the stripping function layer and the light-emitting units on the two sides is tighter; the overall structure of the light-emitting units and the stripping function layer on the substrate can be stripped from the substrate conveniently, the structural integrity of the obtained light-emitting chip is ensured, breakage at the position of an isolation channel of the adjacent light-emitting units is avoided, and the yield and reliability of the light-emitting chip are improved.

There is provided a radio frequency, RF, device (100, 102, 104, 106) comprising: an active semiconductor layer (110) comprising a front surface (112) and a rear surface (114); and an RF transmission line (120) coupled to the front surface (112) of the active semiconductor layer (110), the RF transmission line (120) comprising an active region (121), the active region (121) causing the RF transmission line (120) to comprise a first state in which the RF transmission line (120) has a first radio frequency transmission property, and a second state in which the RF transmission line (120) has a second radio frequency transmission property, wherein the RF transmission line (120) is selectively switchable between the first state and the second state in response to illuminati on of the active semiconductor layer (110) by a light source (210) when in use, and wherein the active semiconductor layer (110) comprises an intrinsic semiconductor material with a thickness, between the front surface (112) and the rear surface (114), of less than 100 microns.

The present invention relates to the technical field of light emitting diodes. Disclosed are a flip-chip LED array and a manufacturing method therefor. The manufacturing method comprises the following steps: (1) fixing one side of a substrate of each flip-chip LED to an adhesive film layer, so as to obtain a chip array; (2) soldering pads of the chip array to solder joints of a packaging substrate; and stripping off the adhesive film layer to obtain a soldered array; (3) removing the substrates and intrinsic semiconductor layers of the flip-chip LEDs of the soldered array, so as to obtain a first intermediate array; (4) forming a reflection layer between adjacent flip-chip LEDs of the first intermediate array, so as to obtain a second intermediate array; and (5) forming a fluorescent layer on the side of the second intermediate array away from the packaging substrate, so as to obtain a finished flip-chip LED array. Implementing the present invention can improve the brightness, the yield and the reliability and prolong the service life of flip-chip LED arrays, and further can shorten the manufacturing process and reduce the product cost.

The present application relates to a solar cell and a preparation method therefor, a photovoltaic module and a photovoltaic system. The solar cell (1) comprises: an intrinsic semiconductor substrate (111), comprising an intrinsic region (111a), a first surface (111b) and a second surface (111c), the first surface (111b) and the second surface (111c) being provided on two opposite sides of the intrinsic semiconductor substrate (111), and the intrinsic region (111a) being provided between the first surface (111b) and the second surface (111c); a first doping structure (112) having a first doping type, the first doping structure (112) being provided on the side of the intrinsic region (111a) close to the first surface (111b); and a second doping structure (113) having a second doping type, the second doping structure (113) being provided on the side of the intrinsic region (111a) close to the second surface (111c), wherein the first doping type is opposite to the second doping type, and the first doping structure (112), the intrinsic region (111a) and the second doping structure (113) form a p-i-n structure.

The invention discloses a back contact cell and a manufacturing method thereof, relates to the field of photovoltaic technology, and is used for reducing the number of defects on one side of a second surface and improving the photoelectric conversion efficiency of the back contact cell. The back contact battery comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer and a second doped semiconductor layer. The first doped semiconductor layer comprises a first doped part and a second doped part, the first doped part is partially located on the first region, and the second doped part is partially located in the isolation region; and the doping concentration of impurities in the second doping part is smaller than that of impurities in the first doping part. And the intrinsic semiconductor layer is formed on the part, except the second doping part, of the isolation region in the direction parallel to the second surface. The second doped semiconductor layer covers the second region, the conduction type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer, and the intrinsic semiconductor layer is used for electrically isolating the first doped semiconductor layer from the second doped semiconductor layer.

A heterojunction cell and a method for preparing same. The heterojunction cell comprises: a semiconductor substrate layer; and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on the surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises: a bottom intrinsic layer; and a wide-band-gap intrinsic layer, which is located on the surface of the side of the bottom intrinsic layer that is away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer being greater than the band gap of the bottom intrinsic layer. The band gap of a wide-band-gap intrinsic layer is larger, and when sunlight irradiates a heterojunction cell, photons, the energy of which is less than that of the band gap of the wide-band-gap intrinsic layer, cannot be subjected to parasitic absorption.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

The application discloses a back contact cell and a manufacturing method thereof, and relates to the technical field of photovoltaics, which is used for preventing leakage between doped semiconductor layers with opposite conductive types in the back contact cell. The back contact cell comprises a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, a second doped semiconductor layer and an insulating mask layer. The first doped semiconductor layer is divided into a first doped part and a second doped part. The second doped part is smaller than the first doped part in impurity doping concentration. The intrinsic semiconductor layer is formed on the part of the second doped part of the isolation area and is integrally formed with the first doped semiconductor layer. The second doped semiconductor layer covers the second area, at least part of the intrinsic semiconductor layer and at least part of the second doped part. The conductive types of the second doped semiconductor layer and the first doped semiconductor layer are opposite, and at least one of the second doped semiconductor layer and the first doped semiconductor layer is a doped crystalline silicon layer.

This invention discloses a nuclear battery based on a three-dimensional through-hole structure and its fabrication method. The nuclear battery includes a three-dimensional through-hole PIN junction semiconductor transducer unit, a radiation source, and an electrode layer. The unit, from top to bottom, consists of a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer. The radiation source is filled in the intrinsic semiconductor through-holes, while the P-type and N-type semiconductor through-holes are filled with electrically insulating materials. The method includes: obtaining a PIN structure on a semiconductor substrate; etching a three-dimensional through-hole array; fabricating a metal seed layer at the bottom of the array; filling the N-type semiconductor through-holes with conductive materials; filling the intrinsic semiconductor through-holes with radiation source material; filling the P-type semiconductor through-holes with electrically insulating materials; and converting the conductive materials in the N-type semiconductor through-holes into electrically insulating materials. This invention improves the energy deposition of radioactive decay particles within the intrinsic layer and the conversion efficiency of radioactive decay energy to electrical energy, thus achieving the fabrication of a high-output performance nuclear battery.

In order to overcome the problems that the existing wide band gap semiconductor material has a large number of spontaneous defects, it is difficult to obtain intrinsic semiconductor and it is difficult to realize reverse type doping, the application discloses a method which can controllably improve the formation energy of spontaneous defects and simultaneously reduce the formation energy of reverse type doping defects by applying voltage, realizes the preparation of intrinsic wide band gap semiconductor material and reverse type doping. The method comprises the following operation steps: during the growth of intrinsic wide band gap semiconductor material and reverse type doping process, a positive bias is applied to the wide band gap semiconductor material which spontaneously forms N type conduction, and a negative bias is applied to the wide band gap semiconductor material which spontaneously forms P type conduction. The application also discloses the application of the above method in the preparation of intrinsic zinc oxide and P type doped zinc oxide.

A device comprising a substrate and a plurality of pixel portions, the plurality of pixel portions including: a first light detecting element located in the pixel portion within an active area; and a second light detecting element located in the pixel portion within an inactive area. The first light detecting element comprises a first lower electrode layer, a first lower impurity semiconductor layer, a first intrinsic semiconductor layer, a first upper impurity semiconductor layer, and a first upper electrode layer; and the second light detecting element comprises a second lower electrode layer, a second lower impurity semiconductor layer, a second intrinsic semiconductor layer, a second upper impurity semiconductor layer, and a second upper electrode layer, wherein the second lower electrode layer is covered by the second lower impurity semiconductor layer and the second intrinsic semiconductor layer.

The invention discloses a longitudinal multi-time programmable memory device and a preparation method thereof, and the method comprises the steps: carrying out the first conduction type ion implantation of intrinsic semiconductor silicon, forming a drain region, a buffer region and a source region, and repairing the crystal damage caused in the ion implantation process through a high-temperature annealing technology; on the basis of a mask, setting an etching stop area through a photoetching step to obtain a first groove and a second groove; performing wet oxidation on the surface of the source region to form an oxide layer, filling polycrystalline silicon to form a floating gate region, and depositing and generating barrier layer metal in the first groove; and forming an insulating layer on the surface of the device, forming a control grid on the surface of the insulating layer, etching barrier layer metal through a mask, electroplating the metal to form a source, and forming a drain on the back surface of the device through a post-processing technology. According to the invention, the gate is controlled to surround the channel of the device, so that the tunneling of carriers into the floating gate region can be realized only by applying very small gate voltage and source voltage.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

The present invention relates to a betavoltaic battery comprising: a substrate; an intrinsic semiconductor unit disposed on the substrate; an N-type semiconductor unit and a P-type semiconductor unit that are disposed on at least a portion of a surface of the intrinsic semiconductor unit and arranged alternately; and beta ray sources that are disposed on the N-type semiconductor unit and the P-type semiconductor unit. The present invention also relates to a method for manufacturing a betavoltaic battery, comprising the steps of: (A) forming an intrinsic semiconductor unit on a substrate; (B) forming an N-type semiconductor unit and a P-type semiconductor unit alternately by irradiating at least a portion of the surface of the intrinsic semiconductor unit with an ion beam; and (C) disposing a beta ray source on the N-type semiconductor unit and the P-type semiconductor unit.

The invention discloses a fast recovery diode and forming detection equipment thereof, and relates to the technical field of fast recovery diodes, the fast recovery diode comprises a main body structure, the main body structure comprises an N-type silicon material substrate layer, and an intrinsic semiconductor layer and a P-type silicon material layer are sequentially arranged on the N-type silicon material substrate layer; wherein an anode end and a cathode end are formed on one side of the main body structure, the anode end is provided with an anode piece, and the cathode end is provided with a cathode piece; before the fast recovery diodes are detected, the high-temperature detection box can be pre-heated, the low-temperature detection box can be pre-cooled, when the fast recovery diodes to be detected are transferred to the corresponding detection box, the fast recovery diodes can quickly reach the temperature interval to be detected, and correspondingly, after one group of fast recovery diodes are detected, the detection time is shortened, and the detection efficiency is improved. And the temperature of the detection box can be kept unchanged, so that the temperature does not need to be adjusted again when the next group of fast recovery diodes is detected.

A semiconductor device according to an embodiment of the present invention may comprise: a semiconductor substrate which is intrinsic or doped with a first dopant of a first type; an epitaxial semiconductor layer which is formed on the semiconductor substrate, is doped with a second dopant of a second type different from the first type, and contains a semiconductor element different from that of the semiconductor substrate; and a diffusion region which is formed in the semiconductor substrate so as to be in contact with the epitaxial semiconductor layer and contains the second dopant.

The application discloses a preparation method of intrinsic semiconductor carbon nanotube material. By using degradable conjugated polymer to replace commonly used separation polymer, separation and purification of semiconductor carbon nanotube and removal of surface polymer can be realized. The polymer used in the application can be quickly degraded under weak acid condition on the basis of ensuring the separation yield and high purity of the semiconductor carbon nanotube, and is decomposed into small molecules, so that the semiconductor carbon nanotube can show its intrinsic performance. Therefore, the semiconductor carbon nanotube material with intrinsic performance can be prepared by using the method of the application, the process is simple, the condition is mild, and the method is stable, efficient and can be widely applied to the carbon-based electronic field.

The application belongs to the technical field of semiconductors, and provides a vertical diode device and a preparation method thereof. The vertical diode device comprises a cathode metal layer, an N-type semiconductor layer, an intrinsic semiconductor layer, a P-type semiconductor layer, an anode metal layer and a P-type doped region. The width of the intrinsic semiconductor layer is less than the width of the N-type semiconductor layer. The P-type doped region is located on the N-type semiconductor layer and is arranged on both sides of the intrinsic semiconductor layer. The thickness of the P-type doped region is less than the thickness of the intrinsic semiconductor layer. By arranging the P-type doped region on both sides of the intrinsic semiconductor layer, the P-type doped region and the intrinsic semiconductor layer form a depletion region, so that the electric field inside the intrinsic semiconductor layer is modulated, the electric field is more uniformly distributed in the intrinsic semiconductor layer, and the reverse breakdown voltage of the diode is improved.

The invention provides a semiconductor device with an improved channel structure and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate; a channel part on the substrate, wherein the channel part comprises a plurality of composite channel layers which are stacked at intervals along the vertical direction; the source / drain parts are respectively positioned on two sides of the channel part in the first direction; and a gate stack extending in a second direction intersecting the first direction and surrounding respective peripheries of the plurality of composite channel layers, in which each composite channel layer includes a first semiconductor layer and a second semiconductor layer surrounding a periphery of the first semiconductor layer, the first semiconductor layer includes an intrinsic semiconductor and the second semiconductor layer includes a heavily doped semiconductor.

The present disclosure belongs to the technical field of radio frequency. Provided are a radio frequency switch and an electronic device, which at least partially solve the problems of the parasitic capacitance of existing radio frequency switches being relatively large and the isolation thereof being low. The radio frequency switch in the present disclosure comprises a substrate, and a semiconductor layer, a first interlayer insulating layer and a connection electrode layer, which are stacked on the substrate in sequence, wherein the semiconductor layer comprises a plurality of N-type semiconductors and a plurality of P-type semiconductors, which are alternately arranged, and an intrinsic semiconductor sandwiched between each N-type semiconductor and each P-type semiconductor; and the connection electrode layer comprises a first connection electrode and a second connection electrode, the first connection electrode comprises a plurality of first branches, the second connection electrode comprises a plurality of second branches, the orthographic projection of one N-type semiconductor on the substrate at least partially overlaps with that of one first branch, the orthographic projection of one P-type semiconductor on the substrate at least partially overlaps with that of one second branch, and at least some of the first branches extend in different directions.

This application relates to a tandem solar cell, its fabrication method, and a photovoltaic module. The tandem solar cell includes a first cell structure and a second cell structure stacked together. The first cell structure includes: a semiconductor substrate having a first surface and a second surface disposed opposite to each other, and a first side surface connected to the first surface and the second surface; a tunneling layer and a first doped semiconductor layer stacked on the first surface and the first side surface; an intrinsic semiconductor layer and a second doped semiconductor layer stacked on the second surface and the first side surface; the surface of the semiconductor substrate has an overlapping region, the overlapping region being at least located on the first side surface, and a portion of the tunneling layer, a portion of the first doped semiconductor layer, a portion of the intrinsic semiconductor layer, and a portion of the second doped semiconductor layer stacked in the overlapping region along a direction away from the semiconductor substrate. Therefore, the tandem solar cell, its fabrication method, and the photovoltaic module provided in this application can improve the passivation effect of the tandem solar cell.

Novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability. Embodiments include a modified NEDMOS IC structure that reduces the maximum E-field between the P-well and the N− drift region, accomplished by creating a region of intrinsic or near-intrinsic semiconductor between the P-well and the N− drift region that locally lowers the maximum E-field and widens the depletion width. The modified NEDMOS IC structure results in a split of the peak of the E-field that would otherwise occur at the junction of the P-well and the N– drift region of a NEDMOS FET. This in turn drops more VDD and therefore lowers the maximum E-field in this region (largely in the OFF state). The threshold voltage VTH is also lowered, which lowers RON in the ON state. The NEDMOS FET simultaneously exhibits improved reliability and an improved transconductance characteristic.