Selective generation method for state vectors of parallel folding counter and hardware circuit for selective generation method

Abstract

The invention relates to a selective generation method for state vectors of a parallel folding counter and a hardware circuit for the selective generation method. The selective generation method is characterized by comprising the following steps of establishing a logical relation among an initial inversion control vector, a folding distance and a corresponding inversion control vector; realizing selective bit replacement on the initial inversion control vector through the decoded output of the folding distance to generate the inversion control vector corresponding to the folding distance; then, performing bitwise exclusive-or operation on the generated inversion control vector and folding seeding vectors in sequence, therefore realizing the selective generation of the state vectors of the folding counter. According to the selective generation method disclosed by the invention, for the given folding seeding vectors and a given folding distance value, the state vector corresponding to the folding distance can be directly generated, and therefore the generation efficiency of deterministic BIST (build-in self-test) test vectors is obviously increased, the generation of redundant state vectors is avoided, and the test time and the test power dissipation of the circuit are reduced.

Description

technical field [0001] The invention relates to a high-efficiency test vector generation technology based on hardware, and belongs to the technical field of integrated circuit testing and computer application. Background technique [0002] With the development of design and process technology, the scale and complexity of integrated circuits are getting higher and higher, and the expansion of test data volume leads to a substantial increase in test application time and test cost. Built-in self-test technology (BIST) can effectively reduce the dependence of testing on automatic testing equipment and reduce testing costs by integrating test vector generation, application and test response analysis circuits inside the chip. At the same time, BIST supports full-speed testing and is conducive to protecting intellectual property rights of integrated circuit testing methods and technologies. [0003] Embedded hardware test vector generation is the key technology of integrated circu...

AI Technical Summary

Problems solved by technology

[0004] The biggest disadvantage of the existing parallel folding counter technology is that for a given folding seed vector, its corresponding state vector can only be generated sequentially

For example, for a folding seed vector with a length greater than or equal to 4, to generate a state vector corresponding to a folding distance of 3, the state vectors corresponding to a folding distance of 0, 1, and 2 must first be sequentially generated, resulting in BIST used for the circuit. Generate a large amount of redundant data, resulting in increased circuit test time and test power consumption

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