Low-power deterministic bist and seed compression method based on single and double jumps

Abstract

The invention relates to the technical field of large-scale digital integrated circuits, and provides a low-power-consumption certainty BIST based on single and double jump and a seed compression method thereof. In order to reduce test power consumption, a novel single and double jump unit and an ROM control signal are applied to generate a certainty seed through single and double hybrid jump, and then certainty test vectors are generated by utilizing a single jump reseeding technology. Meanwhile, the generation number of the certainty test vectors in the reseeding process is constrained by additional arrangement of a 2-bit subtracting counter so as to reduce the number of redundant vectors and reduce test time. Besides, the corresponding seed compression method is also put forward so as to compress area overhead and generate the control signal. The experiment result proves that the test performance, such as test time, the area overhead and test power consumption, of the BIST and the seed compression method can be reduced to a large extent.

Description

technical field [0001] The invention relates to a low-power consumption deterministic BIST and a seed compression method based on single and double transitions, and belongs to the technical field of large-scale digital integrated circuits. Background technique [0002] Today, with the continuous reduction of manufacturing process dimensions and the popularization of low-power technology, the requirements for test power consumption are also increasing. In addition, the correlation between the test vectors is low, which results in much higher power consumption in the test state than in the normal working state, which will eventually affect the reliability of the chip. Therefore, how to reduce the test power consumption has become a research hotspot in recent years. At present, the research directions of low-power built-in self-test are mainly divided into two categories: (1) reducing the test power consumption of the circuit under test (2) reducing the power consumption of th...

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Problems solved by technology

However, compared with the deterministic test technology, the pseudo-random test technology cannot achieve the fault coverage rate that ATPG can achieve. At the same time, in order to achieve a higher fault coverage rate, it needs a longer test time and increases the test power consumption.

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