A Test Data Compression Method for Bipartite Flipping and Folding Technology

Abstract

The invention discloses a test data compression method of bipartite symmetric folding technology, which sorts the vectors in the test set in the descending order of the determined number of bits. The first vector in the sorted test set is selected as a seed to generate a folded set. Compare the vectors in the test set with the vectors in the folded set, if Cj is a definite bit, the value of the bit corresponding to it in Vi is an irrelevant bit or the same definite bit or if the value in Cj is an unrelated bit, Vi The value of the bit corresponding to it in is also an irrelevant bit; then the vector Vi is deleted from the test set. Repeat the above process until the test set is empty, then the obtained seed set S is the result corresponding to the compressed test data T. Compared with the prior art, the present invention has the following advantages: the present invention adopts a non-invasive test data compression method, does not change the structure of the circuit to be tested, does not change the structure of the scan chain in the circuit, uses a seed set to cover the entire test set, and improves Compression ratio reduces test power consumption and shortens test application time.

Description

technical field [0001] The invention relates to a test data compression method in an external built-in self-test method in the field of integrated circuit testing, in particular to a test data compression method using a bipartite turn-over-folding technique. Background technique [0002] According to Moore's Law, the number of transistors integrated on a semiconductor chip doubles approximately every 18 to 24 months. The integration level of SoC is getting higher and higher, which makes the chip size smaller and smaller, the manufacturing cost is continuously reduced, and the performance of the system is greatly improved. However, on the other hand, it brings many problems to the test of the chip. The number of transistors in the chip increases exponentially, and the integration level of IC is getting higher and higher, which makes the test complexity higher and higher. The number of connections and transistors in the circuit is huge, and the manufacturing process is very ...

AI Technical Summary

Problems solved by technology

The advantage is that no additional hardware overhead is required, and the disadvantage is that the coverage of non-model faults is affected

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