Low power consumption LFSR reseeding test compression method facing scanning design

A technology of test compression and reseeding, which is applied in the direction of measuring electricity, measuring devices, and measuring electrical variables, etc., can solve the problems of high test power consumption, achieve the effects of reducing test power consumption, reducing the number, and improving test compression efficiency

Active Publication Date: 2019-03-08
BEIJING UNIV OF TECH
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a low-power consumption LFSR reseeding test compression method for scan design, aiming at the excessively frequent switching activities during the scanning process of the test pattern generated in the LFSR seeding process, resulting in high test power consumption , perform low-power optimized block encoding on the test cube generated by ATPG, and establish a state transition equation system based on this, and use Gaussian Jordan elimination to solve the LFSR seed vector

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Low power consumption LFSR reseeding test compression method facing scanning design
  • Low power consumption LFSR reseeding test compression method facing scanning design
  • Low power consumption LFSR reseeding test compression method facing scanning design

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] Below in conjunction with accompanying drawing and specific embodiment the method of the present invention is further described, and concrete steps of the present invention are as follows:

[0039] Step 1: Refer to attached figure 1 , to obtain the test set for the test circuit. First, 10,000 pseudo-random test patterns are used to test the circuit, and then the LFSR reseeding test is performed for those difficult-to-measure faults, and the test set is determined to be generated by the ATPG tool provided by Atalanta.

[0040] Step 2: Combine the attached figure 1 and figure 1 (a), block preprocessing is performed on the test cube, and different mark bits are added to the data block according to different data types.

[0041] Step 3: According to the attached figure 1, according to the compatibility of the mark bits, the test cubes are grouped and sorted, and the update mark bits are added to determine whether the corresponding mark bits are loaded into the scan chai...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a low power consumption LFSR reseeding test compression method facing scanning design structures. Thus, problems of excessive high test power consumption brought by a traditional LFSR reseeding technology can be solved. Based on an optimized coding algorithm of a test cube, the method can combine with any LFSR reseeding scheme, and be applied to industrial grade super-large-scale integrated circuits and the built-in self-testing of system on chips and functional verification thereof. The basic thinking of the method is as follows: random filling can be performed on don't care bits in the test cube during a LFSR reseeding process, which can trigger excessive high switch switching rates and test power consumption. The method can enhance the logic consistency between adjacent bits in the test cube by optimizing codes, so that test power consumption can be effectively reduced; and seed vector solving difficulty can be reduced by reducing the number of determined bits in the test cube and the number of state equations, so that test data compression rates can be effectively enhanced, and the challenges of testing storage resources can be alleviated.

Description

technical field [0001] The invention belongs to the technical field of very large scale integrated circuits (VLSI), and in particular relates to a scanning design-oriented low-power LFSR reseeding test compression method. Background technique [0002] As microelectronics technology and semiconductor technology enter the era of deep submicron systems, the process size of VLSI is shrinking and the clock frequency is increasing, chip testing is facing more and more challenges. Among them, the increasing data volume and excessive test power consumption are the main problems now. Therefore, many test compression schemes have been proposed to reduce test storage and bandwidth. Existing test data compression techniques mainly include encoding compression, broadcast scan compression and compression based on linear decompression structure. Compared with the first two methods, LFSR-based reseeding technology is adopted by most commercial tools because of its high test compression rat...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318536G01R31/318547
Inventor 袁海英周昌世刘昶张凯郑彤
Owner BEIJING UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products