Test method and device of integrated circuit chip and storage medium

Abstract

The invention aims to provide the test method and device of the integrated circuit chip and the storage medium, so that the test power consumption of the integrated circuit chip can be effectively reduced; in order to achieve the purpose, the testing method and device of the integrated circuit chip and the storage medium are provided, in the testing process, the testing device uses data of all registers as testing signals to be provided for all circuit modules of the integrated circuit chip through the initial shifting action, and therefore the testing accuracy of the integrated circuit chip is improved. And then obtaining output data of each logic circuit in each register through a capture action. Then, the shift operation and the capture operation are repeated, and the test of each logic circuit is performed by comparing the obtained output data of each circuit module with an expected value thereof.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, and in particular, to a method, device, computer equipment and storage medium for testing integrated circuit chips. Background technique [0002] With the rapid development of integrated circuit chip technology, the design requirements for low power consumption, high performance and high reliability are also getting higher and higher. The circuit scan test (Scan test) technology is a common design-for-test (DFT) technology for testing integrated circuit chips. The scan test technology converts the ordinary registers in the sequential circuit into scannable registers, and then serializes the scannable registers into a scan chain, and completes the test of the integrated circuit chip by scanning. The scan test technique first shifts pseudo-random or predetermined test stimulus sources (stimuli) into all scan chains in a shift (Shift) period. Then, in the capture (Capture) cy...

AI Technical Summary

Problems solved by technology

In the scan test mode, the registers in the integrated circuit chip are in a state of frequent flipping, and its power consumption is usually several times larger than that in the normal function mode

In the existing technology, there is a solution to reduce the test power consumption by reducing the clock frequency, but with the increase of the scale of the integrated circuit chip, the reduction of the clock frequency can no longer meet the demand for reducing the test power consumption

At the same time, in the prior art, there is also a method of rearranging the scan chain through digital modeling to reduce test power consumption, but there are still difficulties in applying it to mass production testing

Images