Test access architecture and test access method of digital chip

A digital chip and access method technology, applied in the direction of electronic circuit testing, etc., can solve the problems of large test power consumption, increased wiring overhead, and long test time, and achieve the goal of reducing layout and wiring overhead, reducing test time, and reducing test power consumption Effect

CN114280449APending Publication Date: 2022-04-05BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY +3
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2022-04-05

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Abstract

The embodiment of the invention provides a test access architecture and a test access method of a digital chip, and belongs to the technical field of integrated circuit testing. The architecture comprises N test groups divided by all modules in a digital chip; wherein each test group in the N test groups comprises a plurality of test modules, and the plurality of test modules in each test group are configured to be tested by adopting a distributed test access mechanism; the N test groups are configured to adopt a multi-path selection test access mechanism for testing. The embodiment of the invention is suitable for architecture division in the test process of large-scale digital chips.
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Description

technical field

[0001] The invention relates to the technical field of integrated circuit testing, in particular to a test access architecture and a test access method for large-scale digital chips. Background technique

[0002] With the rapid development of integrated circuit technology, more and more pure digital chips are applied to various fields. In the current pure digital chips, SoC (System On Chip, System on Chip) chips are designed on a large scale and often contain multiple independent cores. Therefore, when testing SoC chips, it is necessary to test the cores in the SoC chip. Modular testing. At present, there are mainly three test structures for modular testing of SoC chips: multiplex structure, daisy chain structure and distributed structure.

[0003] For the above three test structures, especially when testing large-scale SoC chips, there are the following disadvantages: when the multiplex structure tests all the modules in the SoC chip in series, it is easy ...

Examples

Embodiment Construction

[0030] The specific implementation manners of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation manners described here are only used to illustrate and explain the embodiments of the present invention, and are not intended to limit the embodiments of the present invention.

[0031] In the prior art, the multiplex-based test access mechanism belongs to a time-division multiplexing structure, and all modules to be tested are tested serially. by figure 1 The example shown includes the test access structure of three modules to be tested. In order to minimize the test cost, the designer should use the test bandwidth as much as possible to achieve the purpose of reducing the length of the scan chain. Another common test access mechanism is the daisy chain structure, such as figure 2 As shown, in this structure, the scan chain of each module under test i...