Test data compression method based on dichotomy symmetric folding technology

Abstract

The invention discloses a test data compression method based on a dichotomy symmetric folding technology. Vectors in a test set are arranged according to the degressive sequence of the number of determined bits. The first vector in the sequenced test set is selected as a seed, and a folding set is generated. The vectors in the test set are compared with vectors in the folding set, if Cj is the bit of the determined bit, the value of the bit, corresponding to Cj in position, in Vi is the unrelated bit or the same determined bit, or if the value in Cj is the bit of the unrelated bit, the value of the bit, corresponding to Cj in position, in Vi is the unrelated bit; the vector VI is deleted from the test set. The process is repeatedly carried out till the test set is null, and the obtained seed set S is the corresponding result of the test data T through compression. Compared with the prior art, the test data compression method has the following advantages that the non-invasive type test data compression method is adopted, a tested circuit structure is not changed, the structure of a scan chain in the circuit is not changed, the seed set is used for covering the whole test set, the compression rate is increased, the testing power consumption is reduced, and the test application time is shortened.

Description

technical field [0001] The invention relates to a test data compression method in an external built-in self-test method in the field of integrated circuit testing, in particular to a test data compression method of bipartite symmetric folding technology. Background technique [0002] According to Moore's Law, the number of transistors integrated on a semiconductor chip doubles approximately every 18 to 24 months. The integration level of SoC is getting higher and higher, which makes the chip size smaller and smaller, the manufacturing cost is continuously reduced, and the performance of the system is greatly improved. However, on the other hand, it brings many problems to the test of the chip. The number of transistors in the chip increases exponentially, and the integration level of IC is getting higher and higher, which makes the test complexity higher and higher. The number of connections and transistors in the circuit is huge, and the manufacturing process is very comp...

AI Technical Summary

Problems solved by technology

The advantage is that no additional hardware overhead is required, and the disadvantage is that the coverage of non-model faults is affected

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