Primary overturn selection network, overturn sequence decompression structure thereof and decompression method

Abstract

The present invention discloses a primary overturn selection network, an overturn sequence decompression structure thereof and a decompression method. The primary overturn selection network comprises a plurality of combined units of same structures, and each combined unit comprises a D trigger and an XOR gate corresponding to the D trigger. The in-phase input ends of the XOR gates are the input ends of the corresponding combined units, the inverted input ends of the XOR gates are connected with the in-phase input ends, the input ends of the D triggers and the in-phase output ends of the D triggers, and the output ends of the XOR gates are used as the output ends of the corresponding combined units. According to the present invention, the overturn times of the corresponding primary overturn sequence decompression structure is reduced by half, namely the test time is reduced to a half of the original time. In addition, the overturn power consumption of the circuits connected with the triggers is reduced, namely, the test power consumption is also reduced. The present invention also discloses the primary overturn sequence decompression structure having the primary overturn selection network, and the decompression method of the overturn sequence decompression structure.

Description

technical field [0001] The present invention relates to an inversion sequence decompression structure and a decompression method for the inversion sequence decompression structure, in particular to a one-inversion selection network, an inversion sequence decompression structure with the one-inversion selection network, and the inversion sequence decompression The unpacking method for the structure. Background technique [0002] With the increase of integrated circuit integration, the increasing amount of test data has become one of the key problems affecting integrated circuit testing. According to the 2010 ITRS report, to test a chip, in 2009, the requirement for the number of test patterns is only 85, and its compression ratio is only 80; and by 2019, the requirement for the number of test patterns needs to reach 20,370. The requirement for the compression ratio needs to reach 12000. In just ten years, the number of modes has increased to 240 times, and the compression r...

AI Technical Summary

Problems solved by technology

Although the decompression circuit given in the Chinese invention patent 201010046534.X can decompress, it needs 2 clock cycles each time it is expanded from a seed into a test vector, and when generating another test vector from one test vector, the scan flip-flop needs to be flipped twice. times, it will result in increased power consumption of the circuit connected to the flip-flop

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