Large scale integrated circuit test data and method for testing power consumption cooperate optimization

A large-scale integrated circuit and test data technology, applied in the fields of electronic circuit testing, electrical measurement, measurement devices, etc., can solve problems such as hindering the rapid development of system-on-chip SOC testing technology, compressing test data in a single research direction, etc., to reduce scan testing. Power Consumption, Guaranteed Test Coverage, Ease of Implementation

Inactive Publication Date: 2008-04-09
HARBIN INST OF TECH
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Problems solved by technology

[0007] The purpose of the present invention is to solve the problem that most of the existing system-on-chip SOC testing technologies focus on compressing test data or reducing test power consumption as a single research direction, and have not been able to effectively combine t

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  • Large scale integrated circuit test data and method for testing power consumption cooperate optimization
  • Large scale integrated circuit test data and method for testing power consumption cooperate optimization
  • Large scale integrated circuit test data and method for testing power consumption cooperate optimization

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specific Embodiment approach 1

[0018] Specific implementation mode 1: This implementation mode is described in conjunction with FIGS. 1 to 14 . The method steps of this implementation mode are:

[0019] Step 1: Put the test set T D ={t 1 , t 2 ,...tn} is represented as a two-dimensional matrix, each row represents a test vector, a total of n test vectors, each column represents the value assigned to a scan unit in turn, a total of S scan units; calculate the compatibility between the column vectors in the test set , that is, the compatibility between each scanning unit;

[0020] Step 2: Divide the scanning units into K1, K2, and K3 groups by using the clique division method based on the principle of prior merging of isolated points and 2-complete points. The scanning units in each clique are completely compatible. Each group contains only one scanning unit. For the group belonging to the K2 class, each group contains only two scanning units. For the group belonging to the K3 class, each group contains th...

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Abstract

The invention relates to a method collaborating and optimizing the test data and the power consumption of testing large scale integrated circuits. The method relates to the technical field of the large scale integrated circuits and is proposed to resolve the problem that in the prior art of SOC test, no method is available to effectively reduce the test data and the power consumption of test at the same time. The method has the following steps: the compatibility of scanning units of the circuit is analyzed and accordingly the scanning units are classified into three categories; each category of scanning units are connected respectively, and a scanning chain with copying mechanism is built; a set of test vector is adjusted according to the new scanning chain structure; the test set is compressed by the method based on the compression of repeated data and a compressed test set TE is acquired. When in the testing process, the compressed data is fully recovered by a decompression circuit to be tested. The invention discloses a design method for the testability of integrated circuits, and reduces the power consumption of circuits in the testing process, thus ensuring the reliability and testability; furthermore, the invention can effectively reduce the quantity of test data, shorten the test process, and lessen the number of ATE channels.

Description

technical field [0001] The present invention relates to the technical field of large-scale integrated circuits. Background technique [0002] With the rapid development of integrated circuit technology, the integration level of integrated circuits is getting higher and higher, and the functions are becoming more and more complex. Especially with the emergence of system-on-chip (SOC), integrated circuit testing is facing more and more challenges. [0003] On the one hand, these difficulties are reflected in that with the increase of the complexity of integrated circuits, the amount of data required for integrated circuit testing is increasing. For example, in the Loongson-2 chip, about 2G bits of test data are required to complete a complete test. If multiple digital cores are integrated in the chip, the test data will be even larger. The storage space problem brought about by the sharp increase in the amount of test data and the need for multiple test channels will undoubte...

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Application Information

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IPC IPC(8): G01R31/28G01R31/3185
Inventor 彭喜元俞洋乔立岩彭宇刘兆庆
Owner HARBIN INST OF TECH
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