Processor device (202, 302, 402, 502) comprising: a
microprocessor (212) comprising a
microprocessor system agent (214); and a
Field Programmable Gate Array (FPGA) (204, 304, 404, 504), wherein the FPGA (204, 304, 404, 504) comprises: an FPGA
system agent (206, 306, 406, 506) for
processing memory access requests (230) received from the
microprocessor system agent (214) via a
communication link (216, 218), wherein the FPGA system agent (206, 306, 406, 506) and the
communication link (216, 218) are in a coherence region of the microprocessor (212); a
memory controller (207, 316, 416, 508) communicatively coupled to the system agent (206, 306, 406, 506); a high-speed serial interface (208) for connecting the system agent (206, 306, 406, 506) to a
mass storage system (218); wherein the FPGA system agent (206, 306, 406, 506) processes the memory access requests (230) by translating addresses in the memory access requests (230) into the addresses of the
mass storage system (218) and accesses data at the addresses of the
mass storage system (218) through a high-speed serial interface (208).