A screening test method for FPGA programmable logic resources

Abstract

The invention relates to a screening and testing method of FPGA programmable logic resources. The method comprises the following steps of 1 programmable logic resource function design, 2 lookup tabletesting input vector design, 3 RTL-level code emulation, 4 testing result analysis circuit design and 5 module copying and output logic design. According to the screening and testing method of the FPGA programmable logic resources, a testing method based on a BIST is adopted, and the defects that the ATE testing expense is high, and the testing technical difficulty is large are overcome. All LUT modules and DFF modules can be covered only through two sets of matching codes, and the testing efficiency is improved. According to the method, the programmable characteristic of an FPGA chip and richchannel resources and a block random access memory (BRAM) in the chip are fully utilized. The method is simple in implementation step and high in transportability and has certain engineering application value.

Description

technical field [0001] The invention relates to a method for screening and testing FPGA programmable logic resources, which belongs to the technical field of integrated circuits. Background technique [0002] Programmable logic resources are the most important and basic hard core inside Field Programmable Gate Arrays (FPGA). Its main function is to provide the most basic logic operations and data storage functions for digital systems. There are generally hundreds or even tens of thousands of programmable logic modules integrated in the FPGA, and the amount of programmable logic resources is huge. Due to the limitation of test time and test cost, FPGA manufacturers generally do not conduct comprehensive functional tests on common commercial FPGA chips. In the field of high-reliability applications, users need to conduct supplementary screening tests on purchased commercial chips to meet the reliability requirements of the whole machine for components. [0003] Researchers ha...

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Problems solved by technology

[0006] (1) Expensive costs are required to purchase or rent ATE equipment, and it is necessary to develop and design specific ATE test programs and dedicated test circuit boards. At the same time, chip test sockets (sockets) must be used, which increases the number of users to a certain extent. cost to bear

[0007] (2) With the continuous increase of FPGA integration, the scale of the chip is getting larger and larger, and the number of packaged I / O ports is limited. It is becoming more and more difficult to use ATE equipment to perform coverage tests on all programmable logic resources.

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